Very Low Power/Voltage CMOS SRAM
1M X 16 bit
(Dual CE Pins)
BSI
BS616LV1611
FEATURES
• Fully static operation
• Wide Vcc operation voltage : 2.4~5.5V
• Very low power consumption :
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
15uA (Typ.) CMOS standby current
DESCRIPTION
The BS616LV1611 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3.0uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
• High speed access time :
-55
-70
55ns
70ns
The BS616LV1611 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1611 is available in 48-pin BGA package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
OPERATING
PRODUCT FAMILY
Vcc
RANGE
(ICCSB1, Max)
(ICC, Max)
PKG TYPE
TEMPERATURE
55ns : 3.0~5.5V
70ns : 2.7~5.5V
Vcc=3V
70ns
Vcc=5V
70ns
Vcc=3V
Vcc=5V
BS616LV1611FC
BS616LV1611FI
+0 O C to +70O
-40O C to +85O
C
C
2.4V ~ 5.5V
2.4V ~ 5.5V
55 / 70
55 / 70
10uA 110uA
36mA
90mA
92mA
BGA-48-0912
BGA-48-0912
uA
220
20uA
37mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
A2
1
2
3
4
5
6
A1
A0
Address
Input
A
B
C
D
LB
OE
A0
A1
A2
CE2
22
2048
A17
A16
Row
Decoder
Memory Array
2048 x 8192
Buffer
D8
D9
UB
A3
A5
A4
A6
CE1
D1
D0
D2
A15
A14
A13
A12
D10
8192
Data
Input
Buffer
16
16
Column I/O
D0
VSS D11
VCC D12
A17
A7
D3
D4
VCC
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16
512
A16
A15
A13
A10
Data
Output
Buffer
NC
VSS
D6
E
F
16
Column Decoder
D15
D5
D14
D15
A18
D13
A14
CE2
18
CE1
WE
OE
WE
A11
D7
A12
A9
G
H
A.19
A8
Control
Address Input Buffer
UB
LB
A11 A10 A9 A8 A7
A6 A5A18 A19
NC
Vcc
Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
R0201-BS616LV1611
1
Jan.
2004
5秒后页面跳转
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
