bq4285E/L
Enhanced RTC With NVRAM Control
➤ BCD or binary format for clock
General Description
and calendar data
Features
➤ Direct clock/calendar replace-
ment for IBM® AT-compatible
computers and other applications
The CMOS bq4285E/L is a low-power
microprocessor peripheral providing a
time-of-day clock and 100-year calen-
dar with alarm features and battery
operation. Other features include
three maskable interrupt sources,
square wave output, and 114 bytes of
general nonvolatile storage.
➤ Calendar in day of the week, day
of the month, months, and years,
with automatic leap-year adjust-
ment
➤ 114 bytes of general nonvolatile
storage
➤ Time of day in seconds, minutes,
and hours
➤ Enhanced features include:
- 12- or 24-hour format
- System wake-up capability—
alarm interrupt output active
in battery-backup mode
- Optional daylight saving
A 32.768kHz output is available for
sustaining power-management activi-
ties. Wake-up capability is provided by
an alarm interrupt, which is active in
battery-backup mode.
adjustment
- 2.7–3.6V operation (bq4285L);
➤ Programmable square wave out-
4.5–5.5V operation (bq4285E)
put
- 32kHz output for power
➤ Three individually maskable in-
The bq4285E/L write-protects the
clock, calendar, and storage registers
during power failure. A backup bat-
tery then maintains data and oper-
ates the clock and calendar.
management
terrupt event flags:
➤ Automatic backup and write-
- Periodic rates from 122µs to
protect control to external SRAM
500ms
➤ Functionally compatible with the
- Time-of-day alarm once per
DS1285
second to once per day
The bq4285E/L is a fully compatible
real-time clock for IBM AT-
compatible computers and other ap-
plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
- End-of-clock update cycle
➤ 24-pin plastic DIP or SOIC
➤ Less than 0.5 µA load under bat-
tery operation
➤ Selectable Intel or Motorola bus
timing (PLCC), Intel bus timing
(DIP and SOIC)
The bq4285E/L integrates
battery-backup controller to make a
a
➤ 14 bytes for clock/calendar and
control
Pin Names
Pin Connections
AD0–AD7 Multiplexed address/data
input/output
MOT
Bus type select input
(PLCC only )
V
24
1
V
CC
OUT
X
1
23
22
2
3
SQW
CE
CS
AS
DS
R/W
INT
RST
SQW
BC
X1–X2
NC
Chip select input
Address strobe input
Data strobe input
Read/write input
Interrupt request output
Reset input
Square wave output
3V backup cell input
Crystal inputs
X
2
OUT
4
CE
AD
0
21
20
19
18
17
16
15
14
13
IN
5
6
AD
AD
25
24
CE
BC
0
1
IN
5
BC
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
6
INT
RST
DS
V
SS
R/W
7
8
9
10
11
AD
AD
AD
AD
23
22
21
20
19
INT
RST
DS
2
3
4
5
7
8
9
V
SS
NC
R/W
10
11
12
AS
CS
AD
7
No connect
V
SS
CEIN
CEOUT
VOUT
VCC
RAM chip enable input
RAM chip enable output
Supply output
28-Pin PLCC
24-Pin DIP or SOIC
PN428501.eps
PN428502.eps
+5V supply
Jan. 1999 B
1