Datasheet > BQ4011-150

BQ4011-150

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
德州仪器 - TI		静态存储器
页数	文件大小	规格书
13页	755K
描述
32Kx8 Nonvolatile SRAM

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数据手册

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BQ4011-150 数据手册

bq4011/bq4011Y

Write Cycle (T = T

, V

≤ V

)

OPR CCmin

CCmax

-70/-70N

-100

-150/-150N

-200

Min. Max. Min. Max. Min. Max. Min. Max.

Symbol

t_WC

Parameter

Units

Conditions/Notes

Write cycle time

100

150

100

200

150

Chip enable to

end of write

t_CW

(1)

Address valid to

end of write

t_AW

150

Measured from

address valid to

beginning of write. (2)

Ad dr es s s et u p

time

t_AS

Measured from

beginning of write to

end of write. (1)

Write pulse

width

t_WP

130

Write recovery

time (write

cycle 1)

Measured from WE

going high to end of

write cycle. (3)

t_WR1

t_WR2

t_DW

Write recovery

time (write

cycle 2)

Measured from CE

going high to end of

write cycle. (3)

Measured from first

low-to-high transition

of either CE or WE.

Data valid to end

of write

Measured from WE

going high to end of

write cycle. (4)

Data hold time

(write cycle 1)

t_DH1

Measured from CE

going high to end of

write cycle.(4)

Data hold time

(write cycle 2)

t_DH2

Write enabled to

output in high Z

I/O pins are in output

state. (5)

t_WZ

Output active

from end of write

I/O pins are in output

state. (5)

t_OW

Notes:

1. A write ends at the earlier transition of CE going high and WE going high.

2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3. Either t_WR1or t_WR2must be met.

4. Either t_DH1or t_DH2must be met.

5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

Aug. 1993 C

1...3 4 567 8 9...13

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