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BD8113EFV PDF预览

BD8113EFV

更新时间: 2024-02-09 04:20:41
品牌 Logo 应用领域
罗姆 - ROHM /
页数 文件大小 规格书
5页 206K
描述
Silicon Monolithic Integrated Circuit

BD8113EFV 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:HVSSOP, TSSOP24,.3针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
数据输入模式:SERIAL接口集成电路类型:LED DISPLAY DRIVER
JESD-30 代码:R-PDSO-G24JESD-609代码:e2
长度:7.8 mm复用显示功能:NO
功能数量:1区段数:2
端子数量:24最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVSSOP封装等效代码:TSSOP24,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:12 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Display Drivers最大供电电压:30 V
最小供电电压:5 V标称供电电压:12 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Copper (Sn/Cu)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.6 mm
Base Number Matches:1

BD8113EFV 数据手册

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●Cautions on use  
1.Absolute maximum ratings  
We are careful enough for quality control about this IC. So, there is no problem under normal operation, excluding that it exceeds the absolute  
maximum ratings. However, this IC might be destroyed when the absolute maximum ratings, such as impressed voltages or the operating  
temperature range(Topr), is exceeded, and whether the destruction is short circuit mode or open circuit mode cannot be specified. Please take  
into consideration the physical countermeasures for safety, such as fusing, if a particular mode that exceeds the absolute maximum rating is  
assumed.  
2.Reverse polarity connection  
Connecting the power line to the IC in reverse polarity (from that recommended) will damage the part. Please utilize the direction protection  
device as a diode in the supply line.  
3.Power supply line  
Due to return of regenerative current by reverse electromotive force, using electrolytic and ceramic suppress filter capacitors (0.1μF) close to  
the IC power input terminals (Vcc and GND) are recommended. Please note the electrolytic capacitor value decreases at lower temperatures and  
examine to dispense physical measures for safety.  
And, for ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and  
delays. Therefore, give special consideration to power coupling capacitance, width of power wiring, GND wiring, and routing of wiring. Please make  
the power supply lines (where large current flow) wide enough to reduce the resistance of the power supply patterns, because the resistance of  
power supply pattern might influence the usual operation.  
4.GND line  
The ground line is where the lowest potential and transient voltages are connected to the IC.  
5.Thermal design  
Do not exceed the power dissipation (Pd) of the package specification rating under actual operation, and please design enough temperature  
margins.  
6.Short circuit mode between terminals and wrong mounting  
Do not mount the IC in the wrong direction and be careful about the reverse-connection of the power connector. Moreover, this IC might be  
destroyed when the dust short the terminals between them or power supply, GND.  
7.Radiation  
Strong electromagnetic radiation can cause operation failures.  
8.ASO(Area of Safety Operation.)  
Do not exceed the maximum ASO and the absolute maximum ratings of the output driver.  
9.TSD(Thermal shut-down)  
The TSD is activated when the junction temperature (Tj) reaches 175℃(with 25℃ hysteresis), and the output terminal is switched to Hi-z. The  
TSD circuit aims to intercept IC from high temperature. The guarantee and protection of IC are not purpose. Therefore, please do not use this IC  
after TSD circuit operates, nor use it for assumption that operates the TSD circuit.  
10.Inspection by the set circuit board  
The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge electricity in each and all  
process. Moreover, in the inspection process, please turn off the power before mounting the IC, and turn on after mounting the IC. In addition,  
please take into consideration the countermeasures for electrostatic damage, such as giving the earth in assembly process, transportation or  
preservation.  
11.IC terminal input  
This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in this  
P-layer and N-layer of each element. For instance, the resistor or the transistor is connected to the terminal as shown in the figure below. When  
the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the  
parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic  
elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction.  
Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GND(P substrate).  
Please do not apply the voltage to the input terminal when the power-supply voltage is not impressed. Moreover, please impress each input  
terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage is  
impressing.  
Simplified structuIC  
12.Earth wiring pattern  
Use separate ground lines for control signals and high current power driver outputs. Because these high current outputs that flows to the wire  
impedance changes the GND voltage for control signal. Therefore, each ground terminal of IC must be connected at the one point on the set  
circuit board. As for GND of external parts, it is similar to the above-mentioned.  
REV. E  

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