Datasheet > BC2502A

BC2502A

更新时间： 2024-03-03 10:10:46

品牌	Logo	应用领域
台湾合泰/盛群 - HOLTEK		/
页数	文件大小	规格书
14页	623K
描述
Sub-1GHz Low-IF FSK RF Receiver

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中文翻译

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数据手册

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BC2502A 数据手册

BC2502A/BC2502B

Block Diagram

CLDO

Mixer

SD/SCL

I²C

FSK

Demodulator

ADC

RFIN

DO/SDA

BPF

LO GEN

Loop

Filter

CP/PFD

VDDRF

VDD

VCO

MMD

LDOs

POR

Channel

Setting

ΣΔ

Cal

Synthesizer

VSS/EP

Pin Assignment

SD/SCL

TEST

RFIN

AVDD

DO/SDA

CLDO

FREQ

DVDD

VSS/

BC2502A/BC2502B

10 SOP-EP-A

Pin Description

Pin No.

Pin Name

I/O

Description

RX mode shut-down control, should be pulled low in RX Mode

I²C clock input line in Conﬁguration Mode

Not connected, leave ﬂoating

RF LNA input

SD/SCL⁽¹⁾

TEST

RFIN

AVDD

—

PWR

Analog power supply

Crystal oscillator output

Crystal oscillator input

DVDD

PWR

Digital power supply

Pin option for frequency selection:

• GND: 315MHz

• Floating: 433.92MHz

FREQ

• VDD: 868.35MHz (BC2502B only)

CLDO

PWR

LDO output, connected to a bypass capacitor

Demodulated data output in RX Mode

I²C data line in Conﬁguration Mode

—

DO/SDA⁽¹⁾

VSS/EP⁽²⁾

DI/DO

PWR

Exposed pad, must be connected to ground

Legend: DI: Digital Input;

AO: Analog Output;

DO: Digital Output;

PWR: Power.

AI: Analog Input;

Note: 1. The DO/SDA & SD/SCL pins are default connected to a pull-high resistor after a power on reset. After

entering the RX mode, these pull-high resistors are disconnected automatically. An analog debounce

function is added to these two pins.

2. The VSS/EP pin located at the exposed pad.

3.The backside plate of EP shall be well soldered to ground on PCB, otherwise it will downgrade RF performance.

Rev. 1.20

December 05, 2022

123 4 5 6 7...14

中文翻译

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