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ATSAM3U1EA-CU PDF预览

ATSAM3U1EA-CU

更新时间: 2024-11-21 06:38:39
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器和处理器外围集成电路异步传输模式ATM时钟
页数 文件大小 规格书
62页 1565K
描述
AT91ARM Cortex M3-based Microcontrollers

ATSAM3U1EA-CU 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA144,12X12,32
针数:144Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
Factory Lead Time:1 week风险等级:5.73
Is Samacsys:N具有ADC:YES
地址总线宽度:24位大小:32
CPU系列:CORTEX-M3最大时钟频率:12 MHz
DAC 通道:YESDMA 通道:YES
外部数据总线宽度:8JESD-30 代码:S-PBGA-B144
长度:10 mmI/O 线路数量:96
端子数量:144最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA144,12X12,32封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH电源:1.8,3.3 V
认证状态:Not QualifiedRAM(字节):20480
ROM(单词):65536ROM可编程性:FLASH
座面最大高度:1.4 mm速度:12 MHz
子类别:Microcontrollers最大供电电压:1.95 V
最小供电电压:1.62 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:10 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

ATSAM3U1EA-CU 数据手册

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Features  
Core  
– ARM® Cortex®-M3 revision 2.0 running at up to 96 MHz  
– Memory Protection Unit (MPU)  
– Thumb®-2 instruction set  
Memories  
– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,  
dual bank  
– From 16 to 48 Kbytes embedded SRAM with dual banks  
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines  
– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash  
controller with 4 Kbytes RAM buffer and ECC  
AT91ARM  
Cortex M3-based  
Microcontrollers  
System  
– Embedded voltage regulator for single supply operation  
– POR, BOD and Watchdog for safe reset  
– Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768  
kHz for RTC or device clock.  
ATSAM3U Series  
Preliminary  
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default  
Frequency for fast device startup  
– Slow Clock Internal RC oscillator as permanent clock for device clock in low power  
mode  
– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device  
– Up to 17 peripheral DMA (PDC) channels and 4-channel central DMA  
Low Power Modes  
Summary  
– Sleep and Backup modes, down to 2.5 µA in Backup mode  
– Backup domain: VDDBU pin, RTC, 32 backup registers  
– Ultra low power RTC: 0.6 µA  
Peripherals  
– USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints,  
dedicated DMA  
– Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester support) and one  
UART  
– Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC)  
– 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM  
– 4-channel 16-bit PWM (PWMC)  
– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features  
– 8-channel 12-bit 1MSPS ADC with differential input mode and programmable gain  
stage, 8-channel 10-bit ADC  
I/O  
– Up to 96 I/O lines with external interrupt capability (edge or level sensitivity),  
debouncing, glitch filtering and on-die Series Resistor Termination  
– Three 32-bit Parallel Input/Outputs (PIO)  
Packages  
NOTE: This is a summary document.  
The complete document is available on  
the Atmel website at www.atmel.com.  
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm  
– 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm  
– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm  
– 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm  
6430CS–ATARM–09-Apr-10  

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