Features
• High-performance, High-density, Electrically-erasable Programmable Logic Device
• Fully Connected Logic Array with 416 Product Terms
• 15 ns Maximum Pin-to-pin Delay for 5V Operation
• 24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
• D- or T-type Flip-flops
• Product Term or Direct Input Pin Clocking
• Registered or Combinatorial Internal Feedback
• Backward Compatible with ATV2500B/BQ and ATV2500H Software
• Advanced Electrically-erasable Technology
– Reprogrammable
ATF2500C
CPLD Family
Datasheet
– 100% Tested
• 44-lead Surface Mount Package and DIP Package
• Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
• 8 Synchronous Product Terms
• Individual Asynchronous Reset per Macrocell
• OE Control per Macrocell
ATF2500C
• Functionality Equivalent to ATV2500B/BQ and ATV2500H
• 2000V ESD Protection
• Security Fuse Feature to Protect the Code
• Commercial and Industrial Temperature Range Offered
• 10 Year Data Retention
• Pin Keeper Option
• 200 mA Latch-up Immunity
Block Diagram
PLCC/LCC/JLCC
DIP
Pin Configurations
CLK/IN
IN
1
2
3
4
5
6
7
8
9
40 IN
39 IN
Pin Name
Function
IN
38 IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
37 IN
IN
Logic Inputs
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
I/O2
I/O3
I/O4
7
8
9
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
CLK/IN
I/O
Pin Clock and Input
Bi-directional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
I/O 0,2,4...
I/O 1,3,5...
GND
IN 18
IN 19
22 IN
IN 20
21 IN
VCC
+5V Supply
Note:
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required, but are rec-
ommended for improved noise immunity.
Rev. 0777I–PLD–4/03
1