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ATF1504SE-7JC44 PDF预览

ATF1504SE-7JC44

更新时间： 2024-11-03 03:13:55
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
69页 601K
描述
EE PLD, 7.5ns, 64-Cell, CMOS, PQCC44, PLASTIC, LCC-44

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ATF1504SE-7JC44 数据手册

 浏览型号ATF1504SE-7JC44的Datasheet PDF文件第2页浏览型号ATF1504SE-7JC44的Datasheet PDF文件第3页浏览型号ATF1504SE-7JC44的Datasheet PDF文件第4页浏览型号ATF1504SE-7JC44的Datasheet PDF文件第5页浏览型号ATF1504SE-7JC44的Datasheet PDF文件第6页浏览型号ATF1504SE-7JC44的Datasheet PDF文件第7页 
Features  
• 2nd Generation EE PROM-based Complex Programmable Logic Devices  
– VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant  
– 32 - 256 Macrocells with Enhanced Features  
– Pin-compatible with Industry Standard Devices  
– Speeds to 5 ns Maximum Pin-to-pin Delay  
– Registered Operation to 250 MHz  
• Enhanced Macrocells with Logic Doubling™ Features  
– Bury Either Register or COM while Using the Other for Output  
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell  
– 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade  
Logic, Plus 15 more with Foldback Logic  
ATF15xxSE  
Family  
Datasheet  
– D/T/Latch Configurable Flip-flops plus Transparent Latches  
– Global and/or per Macrocell Register Control Signals  
– Global and/or per Macrocell Output Enable  
– Programmable Output Slew Rate per Macrocell  
– Programmable Output Open Collector Option per Macrocell  
– Fast Registered Input from Product Term  
• Enhanced Connectivity  
ATF1502SE(L)  
ATF1504SE(L)  
ATF1508SE(L)  
ATF1516SE(L)  
– Single Level Switch Matrix for Maximum Routing Options  
– Up to 40 Inputs per Logic Block  
• Advanced Power Management Features  
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and  
I/O for µA Level Standby Current for “L” Versions  
– Pin-controlled 1 mA Standby Mode  
– Reduced-power Option per Macrocell  
– Automatic Power Down of Unused Macrocells  
– Programmable Pin-keeper Inputs and I/Os  
• Available in Commercial and Industrial Temperature Ranges  
• Available in All Popular Packages Including PLCC, PQFP and TQFP  
• EE PROM Technology  
Preliminary  
– 100% Tested  
– Completely Reprogrammable  
– 10,000 Program/Erase Cycles  
– 20 Year Data Retention  
– 2000V ESD Protection  
– 200 mA Latch-up Immunity  
• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993  
– Pull-up Option on JTAG Pins TMS and TDI  
• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG  
• PCI-compliant  
• Security Fuse Feature  
Rev. 2401D–PLD–09/02  
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