ATF1504ASZ-25AI44

更新时间： 2024-02-16 02:23:47

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
21页	465K
描述
High- Performance EE CPLD

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ATF1504ASZ-25AI44 数据手册

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Features

• High Density, High Performance Electrically Erasable Complex Programmable Logic

Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 pins

– 7 ns Maximum Pin-to-Pin Delay

– Registered Operation Up To 100 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

High-

Performance

EE CPLD

– D/T/Latch Configurable Flip Flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic utilization by burying a register within a COM output

• Advanced Power Management Features

– Automatic 100 µA Stand-By for “Z” Version

– Pin-Controlled 4 mA Stand-By Mode (Typical)

– Programmable Pin-Keeper Inputs and I/Os

– Reduced-Power Feature Per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-, 68-, and 84-pin PLCC; 44- and 100-pin TQFP; and 100-pin PQFP

• Advanced EE Technology

ATF1504AS

ATF1504ASZ

– 100% Tested

– Completely Reprogrammable

– 100 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-Up Immunity

• JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• 3.3 or 5.0V I/O pins

• Security Fuse Feature

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D - Latch Mode

• Combinatorial Output with Registered Feedback within any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-Keeper” Option

• V_CCPower-Up Reset Option

• Pull-Up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge Controlled Power Down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Description

The ATF1504AS is a high performance, high density Complex Programmable Logic

Device (CPLD) which utilizes Atmel’s proven electrically erasable memory technology.

With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several

Rev. 0950D–07/98

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