Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1504ASV-15AU44

ATF1504ASV-15AU44

更新时间： 2024-02-16 15:12:41

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件异步传输模式 ATM 时钟
页数	文件大小	规格书
31页	559K
描述
Low-voltage, Complex Programmable Logic Device

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ATF1504ASV-15AU44 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	TQFP, TQFP44,.47SQ,32
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
Factory Lead Time：	1 week	风险等级：	8.17
其他特性：	YES	最大时钟频率：	100 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e3	JTAG BST：	YES
长度：	10 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	32
宏单元数：	64	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装等效代码：	TQFP44,.47SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE	电源：	2.5/3.3,3.3 V
可编程逻辑类型：	EE PLD	传播延迟：	15 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

ATF1504ASV-15AU44 数据手册

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ATF1504ASV(L)

All power-down AC characteristic parameters are computed from external input or I/O

pins, with reduced-power bit turned on. For macrocells in reduced-power mode

(reduced-power bit turned on), the reduced-power adder, t_RPA, must be added to the AC

parameters, which include the data paths t_LAD, t_LAC, t_IC, t_ACL, t_ACHand t_SEXP

The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced

on a per macrocell basis. By enabling this power-down option, macrocells that are not

used in an application can be turned down, thereby reducing the overall power con-

sumption of the device.

Each output also has individual slew rate control. This may be used to reduce system

noise by slowing down outputs that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast switching in the design file.

Design Software

Support

ATF1504ASV(L) designs are supported by several industry standard third party tools.

Automated fitters allow logic synthesis using a variety of high-level description lan-

guages and formats.

Power-up Reset

The ATF1504ASV is designed with a power-up reset, a feature critical for state machine

initialization. At a point delayed slightly from V_CCcrossing V_RST, all registers will be ini-

tialized, and the state of each output will depend on the polarity of its buffer. However,

due to the asynchronous nature of reset and uncertainty of how V_CCactually rises in the

system, the following conditions are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving

the clock pin high, and,

3. The clock must remain stable during T_D.

The ATF1504ASV has two options for the hysteresis about the reset level, V_RST, Small

and Large. To ensure a robust operating environment in applications where the device

is operated near 3.0V, Atmel recommends that during the fitting process users configure

the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel

POF2JED users should include the flag “-power_reset” on the command line after “file-

name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis

option selected, the following condition is added:

4. If V_CCfalls below 2.0V, it must shut off completely before the device is turned on

again.

When the Large hysteresis option is active, I_CCis reduced by several hundred micro-

amps as well.

Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504ASV(L) fuse

patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature

remains accessible.

1409J–PLD–6/05

1...6 7 8910 11 12...31

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ATF1504ASV-15JC84	ATMEL	Low-voltage, Complex Programmable Logic Device	获取价格
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