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ATF1504ASV-15JU44-T PDF预览

ATF1504ASV-15JU44-T

更新时间: 2024-02-02 07:44:19
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟输入元件可编程逻辑
页数 文件大小 规格书
30页 847K
描述
EE PLD

ATF1504ASV-15JU44-T 技术参数

生命周期:Active包装说明:QCCJ,
Reach Compliance Code:unknown风险等级:5.69
最大时钟频率:50 MHzJESD-30 代码:S-PQCC-J44
长度:16.5862 mm专用输入次数:
I/O 线路数量:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
可编程逻辑类型:EE PLD传播延迟:15 ns
筛选级别:TS 16949座面最大高度:4.572 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:16.5862 mmBase Number Matches:1

ATF1504ASV-15JU44-T 数据手册

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ATF1504ASV/ATF1504ASVL  
ATF1504ASV(L) 3.3V 64-Macrocell CPLD Data Sheet  
Features  
Enhanced Features  
• High-Density, High-Performance, Electri-  
cally-Erasable Complex Programmable Logic  
Device:  
• Improved Connectivity (Additional Feedback  
Routing, Alternate Input Routing)  
• Output Enable Product Terms  
• Transparent-Latch Mode  
- 3.0V to 3.6V operating range  
- 64 macrocells  
• Combinatorial Output with Registered Feedback  
within any Macrocell  
- 5 product terms per macrocell, expandable  
up to 40 per macrocell  
• Three Global Clock Pins  
- 44 and 100 pins  
• ITD (Input Transition Detection) Circuits on Global  
Clocks, Inputs and I/O  
- 15 ns maximum pin-to-pin delay  
- Registered operation up to 77 MHz  
- Enhanced routing resources  
• Fast Registered Input from Product Term  
• Programmable “Pin-keeper” Option  
• VCC Power-Up Reset Option  
• In-System Programmability (ISP) via JTAG  
• Flexible Logic Macrocell:  
• Pull-Up Option on JTAG Pins (TMS and TDI)  
• Advanced Power Management Features:  
- D/T/Latch configurable flip-flops  
- Global and individual register control signals  
- Global and individual output enable  
- Programmable output slew rate  
- Programmable output open-collector option  
- Edge-controlled power-down  
(ATF1504ASVL)  
- Individual macrocell power option  
- Disable ITD on global clocks  
- Maximum logic utilization by burying a regis-  
ter with a COM output  
Packages  
• Advanced Power Management Features:  
- Automatic 5 µA Standby (ATF1504ASVL)  
- Pin-controlled 100 µA Standby mode (typical)  
• 44-Lead PLCC  
• 44-Lead and 100-Lead TQFP  
- Programmable pin-keeper circuits on inputs  
and I/Os  
Description  
The ATF1504ASV(L) is a high-performance, high-den-  
sity complex programmable logic device (CPLD) that  
utilizes Microchip’s proven electrically-erasable mem-  
ory technology. With 64 logic macrocells and up to  
68 inputs and I/Os, it easily integrates logic from sev-  
eral TTL, SSI, MSI, LSI and classic PLDs. The  
ATF1504ASV(L)’s enhanced routing switch matrices  
increase usable gate count and the odds of successful  
pin-locked design modifications.  
- Reduced-power feature per macrocell  
• Available in Industrial Temperature Range  
• Robust EEPROM Technology:  
- 100% tested  
- Completely reprogrammable  
- 10,000 Program/Erase cycles  
- 20-year data retention  
- 2000V ESD protection  
The ATF1504ASV(L) has up to 64 bidirectional I/O pins  
and four dedicated input pins, depending on the type of  
device package selected. Each dedicated pin can also  
serve as a global control signal (register clock, register  
Reset or output enable). Each of these control signals  
can be selected for use individually within each  
macrocell.  
- 200 mA latch-up immunity  
• JTAG Boundary-Scan Testing to IEEE Std.  
1149.1-1990 and 1149.1a-1993 Supported  
• PCI-Compliant  
• Security Fuse Feature  
• Green (Pb/Halide-Free/RoHS Compliant)  
Package Options  
2019 Microchip Technology Inc.  
DS20006185A-page 1  

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