ATF1504ASV/ATF1504ASVL
PRODUCT TERMS AND SELECT MUX
EXTRA FEEDBACK
Each ATF1504ASV(L) macrocell has five product
terms. Each product term receives as its inputs all
signals from both the global bus and regional bus.
The ATF1504ASV(L) macrocell output can be selected
as registered or combinatorial. The extra buried feed-
back signal can be either combinatorial or a registered
signal regardless of whether the output is combinatorial
or registered. (This enhancement function is automati-
cally implemented by the fitter software.) Feedback of
a buried combinatorial output allows the creation of a
second latch within a macrocell.
The product term select multiplexer (PTMUX) allocates
the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the
optimum macrocell configuration.
I/O CONTROL
OR/XOR/CASCADE LOGIC
The output enable multiplexer (MOE) controls the
output enable signal. Each I/O can be individually
configured as an input, output or for bidirectional
operation. The output enable for each macrocell can be
selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the
I/O macrocells. This selection is automatically done by
the fitter software when the I/O is configured as an
input, all macrocell resources are still available,
including the buried feedback, expander and cascade
logic.
The ATF1504ASV(L)’s logic structure is designed to
efficiently support all types of logic. Within a single
macrocell, all the product terms can be routed to the
OR gate, creating a 5-input AND/OR sum term. With
the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms
with little additional delay.
The macrocell’s XOR gate allows efficient implementa-
tion of compare and arithmetic functions. One input to
the XOR comes from the OR sum term. The other XOR
input can be a product term or a fixed high- or low-level.
For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed
levels allow DeMorgan minimization of product terms.
The XOR gate is also used to emulate T- and JK-type
flip-flops.
GLOBAL BUS/SWITCH MATRIX
The global bus contains all input and I/O pin signals as
well as the buried feedback signal from all
64 macrocells. The switch matrix in each logic block
receives as its inputs all signals from the global bus.
Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
FLIP-FLOP
The ATF1504ASV(L)’s flip-flop has very flexible data
and control functions. The data input can come from
either the XOR gate, from a separate product term or
directly from the I/O pin. Selecting the separate product
term allows creation of a buried registered feedback
within a combinatorial output macrocell. (This feature is
automatically implemented by the fitter software).
FOLDBACK BUS
Each macrocell also generates a foldback product
term. This signal goes to the regional bus and is
available to four macrocells. The foldback is an inverse
polarity of one of the macrocell’s product terms. The
four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with
little additional delay.
In addition to D, T, JK and SR operation, the flip-flop
can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and
is latched when the clock is low.
Programmable Pin-Keeper Option for
Inputs and I/Os
The clock itself can either be one of the Global CLK
Signal (GCK[0:2]) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When
the GCK signal is used as the clock, one of the macro-
cell product terms can be selected as a clock enable.
When the clock enable function is active and the
enable signal (product term) is low, all clock edges are
ignored. The flip-flop’s asynchronous Reset signal (AR)
can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous pre-
set (AP) can be a product term or always off.
The ATF1504ASV(L) offers the option of programming
all input and I/O pins so that pin-keeper circuits can be
utilized. When any pin is driven high or low and then
subsequently left floating, it will stay at that previous
high or low level. This circuitry prevents unused input
and I/O lines from floating to intermediate voltage
levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their
DC power consumption.
2019 Microchip Technology Inc.
DS20006185A-page 5
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