Datasheet > ATF1504ASV-15JU44-T

ATF1504ASV-15JU44-T

更新时间： 2024-02-09 02:25:32

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ATF1504ASV-15JU44-T 技术参数

ATF1504ASV/ATF1504ASVL

Input Diagram

I/O Diagram

All ATF1504ASV(L) also have an optional Power-Down

mode. In this mode, current drops to below 5 mA.

Speed/Power Management

The ATF1504ASV(L) has several built-in speed and

power management features. The ATF1504ASVL con-

tains circuitry that automatically puts the device into a

low-power Standby mode when no logic transitions are

occurring. This not only reduces power consumption

during inactive periods, but also provides proportional

power savings for most applications running at system

speeds below 5 MHz.

When the power-down option is selected, either PD1 or

PD2 pins (or both) can be used to power down the part.

The power-down option is selected in the design

software or design source file. When enabled, the

device goes into power-down when either PD1 or PD2

is high. In the Power-Down mode, all internal logic

signals are latched and held, as are any enabled

outputs.

To further reduce power, each ATF1504ASV(L) macro-

cell has a reduced-power bit feature. This feature

allows individual macrocells to be configured for maxi-

mum power savings. This feature may be selected as

a design option.

All pin transitions are ignored until the PD pin is brought

low. When the power-down feature is enabled, the PD1

or PD2 pin cannot be used as a logic input or output.

However, the pin’s macrocell may still be used to gen-

erate buried foldback and cascade logic signals.

 2019 Microchip Technology Inc.

DS20006185A-page 6

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