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ATF1504ASL-20JL44 PDF预览

ATF1504ASL-20JL44

更新时间: 2024-11-01 14:47:51
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式PC输入元件可编程逻辑
页数 文件大小 规格书
35页 680K
描述
EE PLD, 20ns, PQCC44, PLASTIC, MS-018AC, LCC-44

ATF1504ASL-20JL44 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:LPCC包装说明:PLASTIC, MS-018AC, LCC-44
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.5
最大时钟频率:83.3 MHzJESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.5862 mm
湿度敏感等级:2专用输入次数:
I/O 线路数量:32端子数量:44
最高工作温度:70 °C最低工作温度:
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245可编程逻辑类型:EE PLD
传播延迟:20 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:16.5862 mm
Base Number Matches:1

ATF1504ASL-20JL44 数据手册

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Features  
High-density, High-performance, Electrically-erasable Complex Programmable  
Logic Device  
– 64 Macrocells  
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell  
– 44, 68, 84, 100 Pins  
– 7.5 ns Maximum Pin-to-pin Delay  
– Registered Operation up to 125 MHz  
– Enhanced Routing Resources  
In-System Programmability (ISP) via JTAG  
Flexible Logic Macrocell  
High-  
performance  
Complex  
Programmable  
Logic Device  
– D/T/Latch Configurable Flip-flops  
– Global and Individual Register Control Signals  
– Global and Individual Output Enable  
– Programmable Output Slew Rate  
– Programmable Output Open Collector Option  
– Maximum Logic Utilization by Burying a Register with a COM Output  
Advanced Power Management Features  
– Automatic µA Standby for “L” Version  
– Pin-controlled 1 mA Standby Mode  
– Programmable Pin-keeper Circuits on Inputs and I/Os  
– Reduced-power Feature per Macrocell  
Available in Commercial and Industrial Temperature Ranges  
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP  
Advanced EE Technology  
ATF1504AS  
– 100% Tested  
– Completely Reprogrammable  
– 10,000 Program/Erase Cycles  
ATF1504ASL  
– 20-year Data Retention  
– 2000V ESD Protection  
– 200 mA Latch-up Immunity  
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported  
PCI-compliant  
3.3V or 5.0V I/O Pins  
Security Fuse Feature  
Green (Pb/Halide-fee/RoHS Compliant) Package Options  
Enhanced Features  
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)  
Output Enable Product Terms  
Transparent – Latch Mode  
Combinatorial Output with Registered Feedback within Any Macrocell  
Three Global Clock Pins  
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O  
Fast Registered Input from Product Term  
Programmable “Pin-keeper” Option  
VCC Power-up Reset Option  
Pull-up Option on JTAG Pins TMS and TDI  
Advanced Power Management Features  
– Edge-controlled Power-down “L”  
– Individual Macrocell Power Option  
– Disable ITD on Global Clocks, Inputs and I/O  
Rev. 0950O–PLD–7/05  

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