Datasheet > ATF1504AS-15AL100

ATF1504AS-15AL100

更新时间： 2022-12-01 21:42:41

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
35页	680K
描述
EE PLD, 15ns, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026AED, TQFP-100

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ATF1504AS-15AL100 数据手册

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Features

• High-density, High-performance, Electrically-erasable Complex Programmable

Logic Device

– 64 Macrocells

– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

– 44, 68, 84, 100 Pins

– 7.5 ns Maximum Pin-to-pin Delay

– Registered Operation up to 125 MHz

– Enhanced Routing Resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell

High-

performance

Complex

Programmable

Logic Device

– D/T/Latch Configurable Flip-flops

– Global and Individual Register Control Signals

– Global and Individual Output Enable

– Programmable Output Slew Rate

– Programmable Output Open Collector Option

– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Features

– Automatic µA Standby for “L” Version

– Pin-controlled 1 mA Standby Mode

– Programmable Pin-keeper Circuits on Inputs and I/Os

– Reduced-power Feature per Macrocell

• Available in Commercial and Industrial Temperature Ranges

• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP

• Advanced EE Technology

ATF1504AS

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

ATF1504ASL

– 20-year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• 3.3V or 5.0V I/O Pins

• Security Fuse Feature

• Green (Pb/Halide-fee/RoHS Compliant) Package Options

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• Transparent – Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V_CCPower-up Reset Option

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Features

– Edge-controlled Power-down “L”

– Individual Macrocell Power Option

– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0950O–PLD–7/05

12 3 4 5 6 7...35

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