Datasheet > ATF1502SE-6AC44

ATF1502SE-6AC44

更新时间： 2024-01-05 21:21:18

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
69页	601K
描述
EE PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44

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技术参数
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ATF1502SE-6AC44 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TQFP, TQFP44,.47SQ,32
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
其他特性：	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	最大时钟频率：	200 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G44
JESD-609代码：	e0	JTAG BST：	YES
长度：	10 mm	专用输入次数：
I/O 线路数量：	32	宏单元数：	32
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 32 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TQFP	封装等效代码：	TQFP44,.47SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
峰值回流温度（摄氏度）：	240	电源：	3.3/5,5 V
可编程逻辑类型：	EE PLD	传播延迟：	6 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	10 mm	Base Number Matches：	1

ATF1502SE-6AC44 数据手册

Power-on Reset

The ATF15xx Family devices are designed with a power-on reset, a feature critical for state

machine initialization. At a point delayed slightly from V_CCcrossing V_RST, all registers will be

initialized, and the state of each output will depend on the polarity of its buffer. However, due

to the asynchronous nature of reset and uncertainty of how V_CCactually rises in the system,

the following conditions are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and,

3. The clock must remain stable during T_D.

The ATF15xx Family has two options for the hysteresis about the reset level, V_RST, Small and

Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that

during the fitting process users configure the device with the Power-on Reset hysteresis set to

Large to ensure a robust operating environment.

Power Down of

Unused

To conserve power, Atmel fitters automatically power down all unused macrocells.

Macrocells

Input Transition

Detection/

Automatic Power

Down

The ATF15xxSEL versions provide automatic power-down to µA level stand-by power (the “L”

suffix indicates “Low” power) through Atmel’s patented Input Transition Detection (ITD) cir-

cuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a

low-power standby mode when no logic transitions are occurring. This reduces power con-

sumption during inactive periods, and so provides proportional power savings for most

applications running at system speeds below f_CRITICAL(~5 MHz).

In clocked applications, where the device is operated at a frequency high enough to keep the

device from going into stand-by (above f_CRITICAL), the device will perform at the faster speeds

given in the next faster speed column. These higher speeds can be achieved in combinatorial

designs as well, as long as once activated by an initial input transition, the device continues to

receive input transitions often enough to keep the device from going into standby mode again.

That is, the time between input transitions is less than 1/f_CRITICAL

Reduced-Power

per Macrocell

To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature.

With this feature the designer can reduce power by 50% or more for logic that does not need

to operate at the maximum switching speed. The reduced-power bit may be activated by

changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power

mode (reduced-power bit turned on), the reduced- power adder, t_RPA, must be added to the

AC parameters, which include the data paths t_LAD, t_LAC, t_IC, t_ACL, t_ACHand t_SEXP. All power-down

AC characteristic parameters are computed from external input or I/O pins, with the reduced-

power bit turned on.

Slew Rate Control

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching. The slew rate option is selected in the design source file.

Pin Controlled

Power-down

All ATF15xx Family devices also have an optional pin-controlled power-down mode. When

activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device

goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply

current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as

are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.

Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold

ATF15xxSE Family

2401D–PLD–09/02

1...5 6 789 10 11...69

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与ATF1502SE-6AC44相关器件

型号	品牌	获取价格	描述	数据表
ATF1502SE-6JC44	ATMEL	获取价格	EE PLD, 6ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ATF1502SE-7	ATMEL	获取价格	Family Datasheet
ATF1502SE-7AC44	ATMEL	获取价格	EE PLD, 7.5ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATF1502SE-7AI44	ATMEL	获取价格	EE PLD, 7.5ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATF1502SE-7JC44	ATMEL	获取价格	EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ATF1502SE-7JI44	ATMEL	获取价格	EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ATF1502SEL-15	ATMEL	获取价格	Family Datasheet
ATF1502SEL-15AC44	ATMEL	获取价格	EE PLD, 15ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44
ATF1502SEL-15JC44	ATMEL	获取价格	EE PLD, 15ns, 32-Cell, CMOS, PQCC44, PLASTIC, LCC-44
ATF1502SL	ATMEL	获取价格	Family Datasheet

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