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ATF1502SE-6AC44 PDF预览

ATF1502SE-6AC44

更新时间: 2024-02-26 06:35:35
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟输入元件可编程逻辑
页数 文件大小 规格书
69页 601K
描述
EE PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44

ATF1502SE-6AC44 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP, TQFP44,.47SQ,32
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
其他特性:CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V最大时钟频率:200 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G44
JESD-609代码:e0JTAG BST:YES
长度:10 mm专用输入次数:
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装等效代码:TQFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):240电源:3.3/5,5 V
可编程逻辑类型:EE PLD传播延迟:6 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ATF1502SE-6AC44 数据手册

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Flip-flop  
The ATF15xxSE Family’s flip-flop has very flexible data and control functions. The data input  
can come from either the XOR gate, from a separate product term or directly from the I/O pin.  
Selecting the separate product term allows creation of a buried registered feedback within a  
combinatorial output or vice-versa. (This enhanced function is automatically implemented by  
the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes  
state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode,  
data passes through when the clock is high and is latched when the clock is low.  
When a GCK signal is used as the clock, one of the macrocell product terms can be selected  
as a clock enable. When the clock enable function is active and the enable signal (product  
term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The  
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product  
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-  
nous preset (AP) can be a product term or always off.  
Extra Feedback  
I/O Control  
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The  
extra buried feedback signal can be either combinatorial or registered signal regardless of  
whether the output is combinatorial or registered. (This enhanced function is automatically  
implemented by the fitter software) Feedback of a buried combinatorial output allows the cre-  
ation of a second latch within a macrocell.  
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-  
vidually configured as an input, output or for bi-directional operation. The output enable for  
each macrocell can be selected from the true or compliment of the two output enable pins, a  
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done  
by the fitter software when the I/O is configured as an input, all macrocell resources are still  
available, including the buried feedback, expander and cascade logic.  
The buffer has a fast/slow slew rate option to control EMI and an open-collector option which  
enables the device to provide control signals such as an interrupt that can be asserted by any  
of the several devices.  
Programmable  
Pin-keeper Option  
for Inputs and I/Os  
The ATF15xxSE Family offers the option of programming all input and I/O pins with pin-keeper  
circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin  
keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input  
and I/O lines from floating to intermediate voltage levels, which causes unnecessary power  
consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up  
resistors and eliminate their DC power consumption.  
6
ATF15xxSE Family  
2401D–PLD–09/02  

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