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ATF1502SE-6AC44 PDF预览

ATF1502SE-6AC44

更新时间: 2024-02-02 18:28:42
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟输入元件可编程逻辑
页数 文件大小 规格书
69页 601K
描述
EE PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44

ATF1502SE-6AC44 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP, TQFP44,.47SQ,32
针数:44Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.8
其他特性:CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V最大时钟频率:200 MHz
系统内可编程:YESJESD-30 代码:S-PQFP-G44
JESD-609代码:e0JTAG BST:YES
长度:10 mm专用输入次数:
I/O 线路数量:32宏单元数:32
端子数量:44最高工作温度:70 °C
最低工作温度:组织:0 DEDICATED INPUTS, 32 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装等效代码:TQFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
峰值回流温度(摄氏度):240电源:3.3/5,5 V
可编程逻辑类型:EE PLD传播延迟:6 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Programmable Logic Devices最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ATF1502SE-6AC44 数据手册

 浏览型号ATF1502SE-6AC44的Datasheet PDF文件第6页浏览型号ATF1502SE-6AC44的Datasheet PDF文件第7页浏览型号ATF1502SE-6AC44的Datasheet PDF文件第8页浏览型号ATF1502SE-6AC44的Datasheet PDF文件第10页浏览型号ATF1502SE-6AC44的Datasheet PDF文件第11页浏览型号ATF1502SE-6AC44的Datasheet PDF文件第12页 
ATF15xxSE Family  
latches remain active to ensure that pins do not float to indeterminate levels, further reducing  
system power. All pin transitions are ignored until the PD pin is brought low. When the power-  
down feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output.  
However, the pin’s macrocell may still be used to generate buried foldback and cascade logic  
signals. The power-down option is selected in the design source file.  
Power  
Consumption  
Estimates  
An estimate of power consumption can be made based on typical designs and operation con-  
ditions, but because it is sensitive to these factors, power consumption must be verified with  
actual pattern and operation conditions. The equations given below are based on a pattern of  
16-bit up/down counters in each logic block and may be used to estimate power consumption  
for both operating modes.  
Standby Power  
1. Pstandby = Iccstandby x Vsupply  
Where:  
Iccstandby = the standby current given for the particular device and standby mode (e.g. pin con-  
trolled Power Down)  
Vsupply= the power supply voltage  
Active Power  
2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload  
Where:  
Iccinternal = the internal current estimated from equation 3 below  
Vsupply= the power supply voltage  
Pload = depends on the device output load capacitance and switching frequency on each out-  
put pin.  
Pload and additional power savings at low frequencies using Atmel Input Transition Detection  
(“L” versions) can be estimated according to the methods discussed in the Atmel Application  
Note “Saving Power with Atmel PLDs”  
3.  
I
ccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop  
x
NS)  
Where:  
MCreducedpower = the number of macrocells operating at reduced power (from fitter report file)  
MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are pow-  
ered down.)  
NS = the proportion of logic nodes switching (typically 10-20%)  
fop = the switching frequency  
K1, K2,and K3 = device constants given in the table below.  
Device  
K1 (mA/MC)  
K2 (mA/MC)  
K3 (mA/MC · MHz)  
0.015  
ATF1502SE  
ATF1504SE  
ATF1508SE  
ATF1516SE  
0.6  
0.6  
0.6  
0.6  
0.3  
0.3  
0.3  
0.3  
0.015  
0.015  
0.015  
Note:  
Shaded data is preliminary and subject to change without notice.  
9
2401D–PLD–09/02  

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