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ATA8403C-6AQY PDF预览

ATA8403C-6AQY

更新时间: 2024-10-28 20:10:59
品牌 Logo 应用领域
爱特美尔 - ATMEL 电信光电二极管电信集成电路
页数 文件大小 规格书
12页 1031K
描述
Telecom Circuit, 1-Func, PDSO8, LEAD FREE, TSSOP-8

ATA8403C-6AQY 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:TSSOP, TSSOP8,.19Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
JESD-30 代码:S-PDSO-G8长度:3 mm
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3 V
认证状态:Not Qualified座面最大高度:1.05 mm
子类别:Other Telecom ICs最大压摆率:0.011 mA
标称供电电压:3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:3 mm
Base Number Matches:1

ATA8403C-6AQY 数据手册

 浏览型号ATA8403C-6AQY的Datasheet PDF文件第6页浏览型号ATA8403C-6AQY的Datasheet PDF文件第7页浏览型号ATA8403C-6AQY的Datasheet PDF文件第8页浏览型号ATA8403C-6AQY的Datasheet PDF文件第9页浏览型号ATA8403C-6AQY的Datasheet PDF文件第11页浏览型号ATA8403C-6AQY的Datasheet PDF文件第12页 
7.  
Electrical Characteristics (Continued)  
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.  
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).  
Parameters  
Test Conditions  
Symbol  
Min.  
Typ.  
Max.  
Unit  
fXTO = f0/64  
fXTAL = resonant frequency of the XTAL,  
Oscillator frequency XTO  
(= phase comparator frequency)  
CM 10fF, load capacitance selected  
fXTO  
fXTAL  
ppm  
accordingly  
Tamb = 25°C  
PLL loop bandwidth  
250  
–116  
–80  
kHz  
Referred to fPC = fXT0,  
25kHz distance to carrier  
Phase noise of phase comparator  
In-loop phase noise PLL  
Phase noise VCO  
–110  
–74  
dBc/Hz  
dBc/Hz  
25kHz distance to carrier  
At 1MHz  
At 36MHz  
–89  
–120  
–86  
–117  
dBc/Hz  
dBc/Hz  
Frequency range of VCO  
fVCO  
868  
928  
MHz  
Clock output frequency (CMOS  
microcontroller compatible)  
f0/256  
MHz  
V0h  
V0l  
VS × 0.8  
V
V
Voltage swing at pin CLK  
CLoad 10pF  
VS × 0.2  
110  
7
Series resonance R of the crystal  
Capacitive load at pin XT0  
Rs  
Ω
pF  
FSK modulation frequency rate  
ASK modulation frequency rate  
Duty cycle of the modulation signal = 50%  
Duty cycle of the modulation signal = 50%  
0
0
32  
kHz  
kHz  
50  
Low level input voltage  
High level input voltage  
Input current high  
VIl  
VIh  
IIn  
0.25  
V
V
µA  
ENABLE input  
1.7  
20  
Low level input voltage  
High level input voltage  
Input current high  
VIl  
VIh  
IIn  
0.25  
VS  
5
V
V
µA  
(1)  
PA_ENABLE input  
1.7  
Note:  
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.  
Atmel ATA8403 [DATASHEET]  
10  
4983D–INDCO–08/12  

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