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AT83C24-PRTUL PDF预览

AT83C24-PRTUL

更新时间: 2024-09-16 22:23:27
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
42页 726K
描述
Smart Card Reader Interface with Power Management

AT83C24-PRTUL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC28,.2SQ,20
针数:28Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.6
JESD-30 代码:S-XQCC-N28JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC28,.2SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3/5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Other Microprocessor ICs最大供电电压:5.5 V
最小供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

AT83C24-PRTUL 数据手册

 浏览型号AT83C24-PRTUL的Datasheet PDF文件第3页浏览型号AT83C24-PRTUL的Datasheet PDF文件第4页浏览型号AT83C24-PRTUL的Datasheet PDF文件第5页浏览型号AT83C24-PRTUL的Datasheet PDF文件第7页浏览型号AT83C24-PRTUL的Datasheet PDF文件第8页浏览型号AT83C24-PRTUL的Datasheet PDF文件第9页 
Operational Modes  
TWI Bus Control  
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire  
bus, made up of one clock line and one data line with speeds of up to 400 Kbits per sec-  
ond, based on a byte-oriented transfer format.  
The TWI-bus interface can be used:  
To configure the AT83C24  
To select the operating mode of the card: 1.8V, 3V or 5V  
To configure the automatic activation sequence  
To start or stop sessions (activation and de-activation sequences)  
To initiate a warm reset  
To control the clock to the card in active mode  
To control the clock to the card in stand-by mode (stop LOW, stop HIGH or  
running)  
To enter or leave the card stand-by or power-down modes  
To select the interface (connection to the host I/O / C4/ C8)  
To request the status (card present or not, over-current and out of range  
supply voltage occurrence)  
To drive and monitor the card contacts by software  
To accurately measure the ATR delay when automatic activation is used  
TWI Commands  
Frame Structure  
The structure of the TWI bus data frames is made of one or a series of write and read  
commands completed by STOP.  
Write commands to the AT83C24 have the structure:  
ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)  
Read commands to the AT83C24 have the structure:  
ADDRESS BYTE + DATA BYTE(S)  
The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset  
(hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode  
after the reset.  
Figure 1. Data transfer on TWI bus  
acknowledgement  
from slave  
SDA  
SCL  
Adresse byte  
command  
and/or data  
5
7
8
1
2
3
4
6
9
start condition  
stop condition  
6
AT83C24  
4234E–SCR–09/04  

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