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AT49BV002ANT-70TI PDF预览

AT49BV002ANT-70TI

更新时间: 2024-11-11 03:36:31
品牌 Logo 应用领域
爱特美尔 - ATMEL 光电二极管
页数 文件大小 规格书
19页 261K
描述
Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, PLASTIC, MO-142BD, TSOP1-32

AT49BV002ANT-70TI 数据手册

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Features  
Single Supply for Read and Write: 2.7 to 3.6V  
Fast Read Access Time – 70 ns  
Internal Program Control and Timer  
Sector Architecture  
– One 16K Bytes Boot Block with Programming Lockout  
– Two 8K Bytes Parameter Blocks  
– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)  
Fast Erase Cycle Time – 4 Seconds  
Byte-by-Byte Programming – 30 µs/Byte Typical  
Hardware Data Protection  
DATA Polling for End of Program Detection  
Low Power Dissipation  
2-megabit  
(256K x 8)  
– 15 mA Active Current  
Single 2.7-volt  
Battery-Voltage  
Flash Memory  
– 50 µA CMOS Standby Current  
Typical 10,000 Write Cycles  
Green (Pb/Halide-free) Packaging Option  
1. Description  
The AT49BV002A(N)(T) is a 2.7-volt-only in-system reprogrammable Flash Memory.  
Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with  
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to  
70 ns with power dissipation of just 54 mW over the industrial temperature range.  
AT49BV002A  
AT49BV002AN  
AT49BV002AT  
AT49BV002ANT  
When the device is deselected, the CMOS standby current is less than 50 µA. For the  
AT49BV002AN(T) pin 1 for PLCC package and pin 9 for the TSOP package are no  
connect pins. To allow for simple in-system reprogrammability, the  
AT49BV002A(N)(T) does not require high input voltages for programming. Five-volt-  
only commands determine the read and programming operation of the device. Read-  
ing data out of the device is similar to reading from an EPROM; it has standard CE,  
OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV002A(N)(T)  
is performed by erasing a block of data and then programming on a byte by byte  
basis. The byte programming time is a fast 30 µs. The end of a program cycle can be  
optionally detected by the DATA polling feature. Once the end of a byte program cycle  
has been detected, a new access for a read or program can begin. The typical num-  
ber of program and erase cycles is in excess of 10,000 cycles.  
Not  
Recommended  
for New Design  
The device is erased by executing the erase command sequence; the device inter-  
nally controls the erase operations. There are two 8K byte parameter block sections,  
four main memory blocks, and one boot block.  
The device has the capability to protect the data in the boot block; this feature is  
enabled by a command sequence. The 16K-byte boot block section includes a repro-  
gramming lock out feature to provide data integrity. The boot sector is designed to  
contain user secure code, and when the feature is enabled, the boot sector is pro-  
tected from being reprogrammed.  
In the AT49BV002AN(T), once the boot block programming lockout feature is  
enabled, the contents of the boot block are permanent and cannot be changed. In the  
AT49BV002A(T), once the boot block programming lockout feature is enabled, the  
contents of the boot block cannot be changed with input voltage levels of 5.5 volts or  
less.  
3353G–FLASH–8/05  

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