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AT25020AN-10SN-2.7 PDF预览

AT25020AN-10SN-2.7

更新时间: 2024-11-23 20:45:11
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
18页 392K
描述
EEPROM, 256X8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8

AT25020AN-10SN-2.7 数据手册

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Features  
Serial Peripheral Interface (SPI) Compatible  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Data Sheet Describes Mode 0 Operation  
Medium-voltage and Standard-voltage Operation  
– 2.7 (VCC = 2.7V to 5.5V)  
Extended Temperature Range 40°C to +125°C  
5.0 MHz Clock Rate  
8-byte Page Mode  
Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software  
Data Protection  
Self-timed Write Cycle (10 ms max)  
High Reliability  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP Packages  
SPI Serial  
Extended  
Temperature  
EEPROMs  
1K (128 x 8)  
2K (256 x 8)  
4K (512 x 8)  
Description  
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically-eras-  
able programmable read-only memory (EEPROM) organized as 128/256/512 words of  
8 bits each. The device is optimized for use in many automotive applications where  
low-power and low-voltage operation are essential. The AT25010A/020A/040A is  
available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP  
packages.  
AT25010A  
AT25020A  
AT25040A  
The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed  
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),  
and Serial Clock (SCK). All programming cycles are completely self-timed, and no  
separate erase cycle is required before write.  
Block write protection is enabled by programming the status register with one of four  
blocks of write protection. Separate program enable and program disable instructions  
are provided for additional data protection. Hardware data protection is provided via  
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used  
to suspend any serial communication without resetting the serial sequence.  
8-lead PDIP  
Table 1. Pin Configurations  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
Pin Name  
CS  
Function  
Chip Select  
WP  
GND  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
8-lead SOIC  
SO  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
GND  
VCC  
WP  
WP  
Power Supply  
Write Protect  
GND  
HOLD  
Suspends Serial Input  
8-lead TSSOP  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
WP  
GND  
5087B–SEEPR–1/05  

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