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AT25020B-MAHL-T PDF预览

AT25020B-MAHL-T

更新时间: 2024-11-19 12:26:51
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
27页 1424K
描述
SPI Serial EEPROM

AT25020B-MAHL-T 数据手册

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Features  
Serial Peripheral Interface (SPI) Compatible  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Data Sheet Describes Mode 0 Operation  
Low-voltage and Standard-voltage Operation  
– VCC = 1.8V to 5.5V  
20 MHz Clock Rate (5V)  
8-byte Page Mode  
Block Write Protection  
SPI Serial  
EEPROM  
1K (128x8)  
– Protect 1/4, 1/2, or Entire Array  
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software  
Data Protection  
Self-timed Write Cycle (5 ms max)  
High Reliability  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
2K (256x8)  
Green (Pb/Halogen-free/Rohs Compliant) Packaging Options  
Die Sales: Wafer Form, Waffle Pack, Bumped Wafers  
4K (512x8)  
Description  
AT25010B  
AT25020B  
AT25040B  
The AT25010B/020B/040B provides 1024/2048/4096 bits of serial electrically eras-  
able programmable read-only memory (EEPROM) organized as 128/256/512 words  
of 8 bits each. The device is optimized for use in many industrial and commercial  
applications where low-power and low-voltage operation are essential. The  
AT25010B/020B/040B is available in space saving, JEDEC SOIC, UDFN, TSSOP,  
XDFN and VFBGA packages.  
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and accessed  
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),  
and Serial Clock (SCK). All programming cycles are completely self-timed, and no  
separate erase cycle is required before write.  
Block write protection is enabled by programming the status register with one of four  
blocks of write protection. Separate Program Enable and Program disable instructions  
are provided for additional data protection. Hardware data protection is provided via  
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used  
to suspend any serial communication without resetting the serial sequence.  
Table 0-1.  
Pin Configuration  
SOIC, TSSOP  
Pin Name  
CS  
Function  
CS  
SO  
VCC  
1
2
3
4
8
7
6
5
Chip Select  
HOLD  
SCK  
SI  
WP  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
GND  
SO  
8-lead UDFN, XDFN  
8-ball VFBGA  
GND  
VCC  
8
7
6
5
1
2
3
4
VCC  
HOLD  
SCK  
SI  
8
7
6
5
1
2
3
4
CS  
VCC  
HOLD  
SCK  
SI  
CS  
Power Supply  
Write Protect  
SO  
SO  
WP  
WP  
GND  
WP  
GND  
HOLD  
Suspends Serial Input  
8707B–SEEPR–3/10  
Bottom View  
Bottom View  

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