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AT24C256B_07 PDF预览

AT24C256B_07

更新时间： 2024-11-18 04:49:43
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
21页 712K
描述
Two-wire Serial EEPROM 256K (32,768 x 8)

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中文翻译

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AT24C256B_07 数据手册

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Features  
• Low-voltage and Standard-voltage Operation  
– 1.8 (VCC = 1.8V to 3.6V)  
• Internally Organized as 32,768 x 8  
• Two-wire Serial Interface  
• Schmitt Trigger, Filtered Inputs for Noise Suppression  
• Bidirectional Data Transfer Protocol  
• 1 MHz (3.6V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility  
• Write Protect Pin for Hardware and Software Data Protection  
• 64-byte Page Write Mode (Partial Page Writes Allowed)  
• Self-timed Write Cycle (5 ms Max)  
• High Reliability  
Two-wire Serial  
EEPROM  
– Endurance: One Million Write Cycles  
– Data Retention: 40 Years  
• Lead-free/Halogen-free Devices Available  
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead MAP, 8-lead Ultra Thin  
Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages  
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers  
256K (32,768 x 8)  
Description  
AT24C256B  
The AT24C256B provides 262,144 bits of serial electrically erasable and programma-  
ble read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The  
device’s cascadable feature allows up to eight devices to share a common two-wire  
bus. The device is optimized for use in many industrial and commercial applications  
where low-power and low-voltage operation are essential. The devices are available  
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead Ultra  
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is  
available in a 1.8V (1.8V to 3.6V) version.  
Table 1. Pin Configurations  
8-lead PDIP  
8-lead SOIC  
Pin Name  
A0–A2  
SDA  
Function  
1
2
3
4
8
7
6
5
8
7
6
5
A0  
A1  
VCC  
WP  
A0  
A1  
1
2
3
4
VCC  
WP  
Address Inputs  
Serial Data  
Serial Clock Input  
Write Protect  
No Connect  
Ground  
A2  
SCL  
SDA  
A2  
SCL  
SDA  
GND  
GND  
SCL  
8-lead dBGA2  
8-lead TSSOP  
WP  
VCC  
8
7
6
5
1
2
3
4
A0  
NC  
8
A0  
1
2
3
4
VCC  
WP  
SCL  
SDA  
A1  
7
6
5
A1  
A2  
WP  
GND  
A2  
SCL  
SDA  
GND  
GND  
Bottom View  
8-lead Ultra Thin SAP  
8-lead MAP  
VCC  
WP  
8
7
6
5
1
2
3
4
A0  
VCC  
8
7
6
5
1
A0  
A1  
WP  
SCL  
SDA  
2
3
4
A1  
SCL  
SDA  
A2  
A2  
GND  
GND  
Bottom View  
Bottom View  
Rev. 5080B–SEEPR–1/07  
1234567...21

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