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AT-30533TR1 PDF预览

AT-30533TR1

更新时间: 2024-09-15 22:14:51
品牌 Logo 应用领域
安捷伦 - AGILENT 晶体晶体管
页数 文件大小 规格书
10页 101K
描述
Low Current, High Performance NPN Silicon Bipolar Transistor

AT-30533TR1 数据手册

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Low Current, High Performance  
NPN Silicon Bipolar Transistor  
Technical Data  
AT-30511  
AT-30533  
Features  
Description  
Optimized performance at 2.7 V  
makes these devices ideal for use  
in900MHz, 1.8GHz, and2.4GHz  
battery operated systems as an  
LNA, gain stage, buffer, oscillator,  
or active mixer. Typical amplifier  
designs at 900 MHz yield 1.3 dB  
noise figures with 13 dB or more  
associated gain at a 2.7 V, 1 mA  
bias. Voltage breakdowns are high  
enough for use at 5 volts. High  
gain capability at 1 V, 1 mA makes  
these devices a good fit for  
• High Performance Bipolar  
Transistor Optimized for  
Low Current, Low Voltage  
Operation  
• 900 MHz Performance:  
AT-30511:1.1dBNF,16 dB GA  
AT-30533:1.1dBNF,13 dB GA  
• Characterized for End-Of-  
Life Battery Use (2.7 V)  
• SOT-23 and SOT-143 SMT  
Plastic Packages  
Hewlett-Packard’sAT-30511and  
AT-30533arehighperformance  
NPN bipolar transistors that have  
been optimized for maximum fT at  
low voltage operation, making  
them ideal for use in battery  
powered applications in wireless  
markets. The AT-30533 uses the 3  
leadSOT-23, whiletheAT-30511  
places the same die in the higher  
performance 4 lead SOT-143. Both  
packages are industry standard,  
and compatible with high volume  
surface mount assembly  
• Tape-And-Reel Packaging  
Option Available[1]  
900 MHzpagerapplications.  
The AT-3 series bipolar transistors  
are fabricated using an optimized  
version of Hewlett- Packard’s  
10 GHzf T,30GHzfMAX Self-  
Aligned-Transistor (SAT) process.  
The die are nitride passivated for  
surface protection. Excellent  
device uniformity, performance  
and reliability are produced by the  
use of ion-implantation, self-  
alignment techniques, and gold  
metalization in the fabrication of  
these devices.  
techniques.  
Outline Drawing  
The 3.2 micron emitter-to-emitter  
pitch and reduced parasitic design  
of these transistors yields  
extremely high performance  
products that can perform a multi-  
plicity of tasks. The 5 emitter  
finger interdigitated geometry  
yields an extremely fast transistor  
with high gain and low operating  
currents.  
EMITTER COLLECTOR  
305  
BASE  
EMITTER  
SOT-143 (AT-30511)  
COLLECTOR  
305  
BASE  
EMITTER  
SOT-23 (AT-30533)  
Note:  
1. Refer to “Tape-and-Reel Packaging for  
Semiconductor Devices”.  
4-23  
5965-8918E  

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