Datasheet > ASM5P23SS05A-1H-08-ST

ASM5P23SS05A-1H-08-ST

更新时间： 2024-11-25 03:38:59

品牌	Logo	应用领域
PULSECORE		光电二极管
页数	文件大小	规格书
15页	663K
描述
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8

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ASMP5P23SS09A

ASMP5P23SS05A

November 2003

rev 1.1

3.3V Peak Reducing Zero Delay Buffer

General Features

typically 1000 times slower than the fundamental clock, the

spread spectrum process has negligible impact on system

performance while giving significant cost savings. Alliance

offers options with different spreading patterns with more

spread and greater EMI reduction.

10 MHz to 133- MHz operating range, compatible

with CPU and PCI bus frequencies.

•

EMI reduced output with on-chip EMI reduction

capability.

•

Zero input - output propagation delay.

Multiple low-skew outputs.

The -1H version of the ASM5P23SXXA operates at up to

133- MHz frequencies, and has higher drive than the -1

devices. All parts have on-chip PLLs that lock to an input

clock on the REF pin. The PLL feedback is on-chip and is

obtained from the CLKOUT pad.

•

Output-output skew less than 250 ps.

Device-device skew less than 700 ps.

One input drives 9 outputs, grouped as 4 + 4 + 1

(ASM5P23SS09A).

One input drives 5 outputs (ASM5P23SS05A).

•

Less than 200 ps cycle-to-cycle jitter is compatible with

The ASM5P23SS09A has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. If all the output clocks are

not required, Bank B can be three-stated. The select input

also allows the input clock to be directly applied to the

outputs for chip and system testing purposes.

Pentium^®based systems.

Test Mode to bypass PLL (ASM5P23SS09A only, refer

Select Input Decoding Table).

Available in 16-pin, 150-mil SOIC, 4.4 mm TSSOP,

and 150-mil SSOP packages (ASM5P23SS09A) or in

8-pin, 150-mil SOIC package (ASM5P23SS05A).

3.3V operation, advanced 0.35µ CMOS technology.

•

Multiple ASM5P23SS09A and ASM5P23SS05A devices

can accept the same input clock and distribute it. In this

case the skew between the outputs of the two devices is

guaranteed to be less than 700ps. All outputs have less

than 200 ps of cycle-to-cycle jitter. The input and output

propagation delay is guaranteed to be less than 250 ps,

and the output to output skew is guaranteed to be less than

250ps.

Functional Description

ASM5P23SS09A is a versatile, spread spectrum output,

3.3V zero-delay buffer designed to distribute high-speed

clocks with EMI suppression capability. It is available in a

16-pin package. The ASM5P23SS05A is the eight-pin

version of the ASM5P23SS09A. It accepts one reference

input and drives out five low-skew clocks. The

ASM5P23SXXA family incorporates the latest advances in

PLL spread spectrum techniques to greatly reduce the

peak EMI by modulating the output frequency with a low

frequency carrier. The ASM5P23SXXA allows significant

system cost savings by reducing the number of circuit

board layers and shielding that are traditionally required to

pass EMI regulations. Because the modulating frequency is

The ASM5P23SS09A and the ASM5P23SS05A are

available in two different configurations, as shown in the

ordering information table. The ASM5P23SXXA-1 is the

base part. The ASM5P23SXXA-1H is the high drive version

of the -1 and its rise and fall times are much faster than -1

part.

Peak Reducing

MUX

CLKOUT

CLKA1

CLKA2

CLKA3

PLL

Block Diagram

REF

Peak Reducing

CLKOUT

REF

PLL

CLK1

CLK2

CLK3

CLK4

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

ASM5P23SS05A

ASM5P23SS09A

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...15

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与ASM5P23SS05A-1H-08-ST相关器件

型号	品牌	获取价格	描述	数据表
ASM5P23SS05A-1H-08-TR	PULSECORE	获取价格	PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, TSSOP-8
ASM5P23SS05A-1H-08-TT	PULSECORE	获取价格	PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, TSSOP-8
ASM5P23SS08A-1-16-SR	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-1-16-ST	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-1-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-1-16-TT	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-1H-16-SR	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-1H-16-ST	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-1H-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-1H-16-TT	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS

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