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ASM5P23SS08A-3-16-ST PDF预览

ASM5P23SS08A-3-16-ST

更新时间： 2024-11-25 03:00:19
品牌 Logo 应用领域
PULSECORE 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 707K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16

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ASM5P23SS08A-3-16-ST 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：0.150 INCH, SOIC-16Reach Compliance Code：unknown
风险等级：5.18输入调节：STANDARD
JESD-30 代码：R-PDSO-G16长度：9.89 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：16
实输出次数：8最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.4 ns座面最大高度：1.73 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mm最小 fmax：133.3 MHz

ASM5P23SS08A-3-16-ST 数据手册

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November 2003  
rev 1.1  
ASM5P23SS08A  
3.3V Zero Delay Buffer  
be driven to FBK pin, and can be obtained from one of the  
outputs. The input-to-input propogation delay is guaranteed  
to be less than 350ps, and the output-to-output skew is  
guaranteed to be less than 250ps.  
General Features  
•
•
•
Zero input - output propagation delay, adjustable by  
capacitive load on FBK input.  
EMI reduced output with on-chip EMI reduction  
capability.  
Multiple configurations  
Configurations Table”.  
The ASM5P23SS08A has two banks of four outputs each,  
which can be controlled by the select inputs as shown in  
the Select Input Decoding Table. If all the output clocks are  
not required, Bank B can be three-stated. The select input  
also allows the input clock to be directly applied to the  
outputs for chip and system testing purposes.  
-
Refer “ASM5P23SS08A  
•
•
Input frequency range : 10MHz to 133MHz  
Multiple low-skew outputs.  
•
•
•
Output-output skew less than 200 ps.  
Device-device skew less than 700 ps.  
Two banks of four outputs, three-stateable by two  
select inputs.  
Multiple ASM5P23SS08A devices can accept the same  
input clock and distribute it. In this case the skew between  
the outputs of the two devices is guaranteed to be less than  
700ps.  
•
•
•
•
•
Less than 200 ps cycle-to-cycle jitter (-1, -1H, -4, -5H).  
Available in 16-pin SOIC and TSSOP packages.  
3.3V operation.  
Advanced 0.35µ CMOS technology.  
Industrial temperature available.  
The ASM5P23SS08A is available in five different  
configurations (Refer “ASM5P23SS08A Configurations  
Table). The ASM5P23SS08A-1 is the base part, where the  
output frequencies equal the reference if there is no  
counter in the feedback path. The ASM5P23SS08A-1H is  
the high-drive version of the -1 and the rise and fall times  
on this device are much faster.  
Functional Description  
ASM5P23SS08A is a versatile, spread spectrum output,  
3.3V zero-delay buffer designed to distribute high-speed  
clocks with EMI supression capability. It is available in a  
16-pin package. The ASM5P23SS08A family incorporates  
the latest advances in PLL spread spectrum techniques to  
greatly reduce the peak EMI by modulating the output  
The ASM5P23SS08A-2 allows the user to obtain 2X and  
1X frequencies on each output bank. The exact  
configuration and output frequencies depends on which  
output drives the feedback pin. The ASM5P23SS08A-3  
allows the user to obtain 4X and 2X frequencies on the  
outputs.  
frequency with  
a
low frequency carrier  
.
The  
ASM5P23SS08A allows significant system cost savings by  
reducing the number of circuit board layers and shielding  
that are traditionally required to pass EMI regulations.  
Because the modulating frequency is typically 1000 times  
slower than the fundamental clock, the spread spectrum  
process has negligible impact on system performance  
while giving significant cost savings. Alliance offers options  
with different spreading patterns with more spread and  
greater EMI reduction.  
The ASM5P23SS08A-4 enables the user to obtain 2X  
clocks on all outputs. Thus, the part is extremely versatile,  
and can be used in a variety of applications.  
The ASM5P23SS08A-5H is a high-drive version with  
REF/2 on both banks.  
The part has an on-chip PLL whick locks to an input clock  
presented on the REF pin. The PLL feedback is required to  
Alliance Semiconductor  
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com  
Notice: The information in this document is subject to change without notice.  
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与ASM5P23SS08A-3-16-ST相关器件

型号 品牌 获取价格 描述 数据表
ASM5P23SS08A-3-16-TR PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-3-16-TT PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-4-16-SR PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-4-16-ST PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-4-16-TR PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-4-16-TT PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-5H-16-SR PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-5H-16-ST PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH,
ASM5P23SS08A-5H-16-TR PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-5H-16-TT PULSECORE

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 		PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS

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