Datasheet > ASM5P23SS08A-5H-16-ST

ASM5P23SS08A-5H-16-ST

更新时间： 2024-11-25 03:15:35

品牌	Logo	应用领域
PULSECORE		光电二极管
页数	文件大小	规格书
16页	707K
描述
PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, SOIC-16

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ASM5P23SS08A-5H-16-ST 数据手册

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第2页

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第3页

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第4页

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第5页

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第6页

浏览型号ASM5P23SS08A-5H-16-ST的Datasheet PDF文件第7页

November 2003

rev 1.1

ASM5P23SS08A

3.3V Zero Delay Buffer

be driven to FBK pin, and can be obtained from one of the

outputs. The input-to-input propogation delay is guaranteed

to be less than 350ps, and the output-to-output skew is

guaranteed to be less than 250ps.

General Features

•

Zero input - output propagation delay, adjustable by

capacitive load on FBK input.

EMI reduced output with on-chip EMI reduction

capability.

Multiple configurations

Configurations Table”.

The ASM5P23SS08A has two banks of four outputs each,

which can be controlled by the select inputs as shown in

the Select Input Decoding Table. If all the output clocks are

not required, Bank B can be three-stated. The select input

also allows the input clock to be directly applied to the

outputs for chip and system testing purposes.

Refer “ASM5P23SS08A

•

Input frequency range : 10MHz to 133MHz

Multiple low-skew outputs.

•

Output-output skew less than 200 ps.

Device-device skew less than 700 ps.

Two banks of four outputs, three-stateable by two

select inputs.

Multiple ASM5P23SS08A devices can accept the same

input clock and distribute it. In this case the skew between

the outputs of the two devices is guaranteed to be less than

700ps.

•

Less than 200 ps cycle-to-cycle jitter (-1, -1H, -4, -5H).

Available in 16-pin SOIC and TSSOP packages.

3.3V operation.

Advanced 0.35µ CMOS technology.

Industrial temperature available.

The ASM5P23SS08A is available in five different

configurations (Refer “ASM5P23SS08A Configurations

Table). The ASM5P23SS08A-1 is the base part, where the

output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P23SS08A-1H is

the high-drive version of the -1 and the rise and fall times

on this device are much faster.

Functional Description

ASM5P23SS08A is a versatile, spread spectrum output,

3.3V zero-delay buffer designed to distribute high-speed

clocks with EMI supression capability. It is available in a

16-pin package. The ASM5P23SS08A family incorporates

the latest advances in PLL spread spectrum techniques to

greatly reduce the peak EMI by modulating the output

The ASM5P23SS08A-2 allows the user to obtain 2X and

1X frequencies on each output bank. The exact

configuration and output frequencies depends on which

output drives the feedback pin. The ASM5P23SS08A-3

allows the user to obtain 4X and 2X frequencies on the

outputs.

frequency with

low frequency carrier

The

ASM5P23SS08A allows significant system cost savings by

reducing the number of circuit board layers and shielding

that are traditionally required to pass EMI regulations.

Because the modulating frequency is typically 1000 times

slower than the fundamental clock, the spread spectrum

process has negligible impact on system performance

while giving significant cost savings. Alliance offers options

with different spreading patterns with more spread and

greater EMI reduction.

The ASM5P23SS08A-4 enables the user to obtain 2X

clocks on all outputs. Thus, the part is extremely versatile,

and can be used in a variety of applications.

The ASM5P23SS08A-5H is a high-drive version with

REF/2 on both banks.

The part has an on-chip PLL whick locks to an input clock

presented on the REF pin. The PLL feedback is required to

Alliance Semiconductor

2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...16

中文翻译

下载PDF

与ASM5P23SS08A-5H-16-ST相关器件

型号	品牌	获取价格	描述	数据表
ASM5P23SS08A-5H-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS08A-5H-16-TT	PULSECORE	获取价格	PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSS
ASM5P23SS09A-1-16-SR	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-1
ASM5P23SS09A-1-16-ST	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-1
ASM5P23SS09A-1-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16
ASM5P23SS09A-1-16-TT	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16
ASM5P23SS09A-1H-16-SR	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-1
ASM5P23SS09A-1H-16-ST	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-1
ASM5P23SS09A-1H-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16
ASM5P23SS09A-1H-16-TT	PULSECORE	获取价格	PLL Based Clock Driver, 9 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 MM, TSSOP-16

与ASM5P23SS08A-5H-16-ST相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM5P23SS08A-5H-16-ST

ASM5P23SS08A-5H-16-ST 数据手册

与ASM5P23SS08A-5H-16-ST相关器件

与ASM5P23SS08A-5H-16-ST相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ASM5P23SS08A-5H-16-ST

ASM5P23SS08A-5H-16-ST 数据手册

与ASM5P23SS08A-5H-16-ST相关器件

与ASM5P23SS08A-5H-16-ST相关文章

您还可以找

您在本页遇到什么问题？