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ASM3P2274A-06-OR PDF预览

ASM3P2274A-06-OR

更新时间: 2024-11-12 04:08:43
品牌 Logo 应用领域
PULSECORE 光电二极管
页数 文件大小 规格书
8页 313K
描述
Clock Generator, 120MHz, CMOS, PDSO6, TSOT-23, 6 PIN

ASM3P2274A-06-OR 数据手册

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November 2005  
rev 0.3  
ASM3P2274A  
Low Power 4X Multiplier EMI Reduction IC  
Features  
The ASM3P2274A uses the most efficient and optimized  
modulation profile approved by the FCC and is  
implemented by using a proprietary all digital method.  
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Generates a 4X EMI optimized clock signal at the  
output.  
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Integrated loop filter components.  
Operates with a 3.3 / 2.5V Supply.  
Low power CMOS design.  
Input frequency range: 12MHz to 30MHz for 2.5V.  
: 12MHz to 30MHz for 3.3V.  
Frequency deviation: -1.5% (Typ) @66MHz Output  
Frequency.  
Available in 6-pin TSOT-23 Package.  
The ASM3P2274A modulates the output of a single PLL  
in order to “spread” the bandwidth of a synthesized clock,  
and more importantly, decreases the peak amplitudes of  
its harmonics. This results in significantly lower system  
EMI compared to the typical narrow band signal produced  
by oscillators and most frequency generators. Lowering  
EMI by increasing a signal’s bandwidth is called ‘spread  
spectrum clock generation’.  
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Product Description  
Applications  
The ASM3P2274 is  
a versatile Spread Spectrum  
The ASM3P2274A is targeted towards all portable  
devices with very low power requirements like MP3  
players,MFP, LCD Panel Module and digital still cameras.  
Frequency Modulator designed specifically for a wide  
range of clock frequencies. It provides a 4x Spread  
Spectrum Modulated output from an input clock source.  
The ASM3P2274A reduces electromagnetic interference  
(EMI) at the clock source, allowing system wide reduction  
of EMI of all clock dependent signals. The ASM3P2274A  
allows significant system cost savings by reducing the  
number of circuit board layers ferrite beads, shielding  
that are traditionally required to pass EMI regulations.  
Key Specifications  
Description  
Specification  
VDD = 3.3V / 2.5V  
Supply voltages  
Cycle-to-Cycle Jitter  
Output Duty Cycle  
360pS (Typ)  
45/55%  
Modulation Rate Equation  
Frequency Deviation  
FIN/640  
-1.5% (Typ) @ 66MHz Output  
Block Diagram  
VDD  
PD  
PLL  
Modulation  
XIN/CLKIN  
XOUT  
Crystal  
Frequency  
Divider  
Oscillator  
Output  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
ModOUT  
VSS  
Alliance Semiconductor  
2575 Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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