Datasheet > 微控制器和处理器 > 时钟发生器> ASM3P2474AF-08SR

ASM3P2474AF-08SR

更新时间： 2024-11-10 22:15:43

品牌	Logo	应用领域
ALSC		晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数	文件大小	规格书
10页	172K
描述
Low Power Peak EMI Reducing Solution

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中文翻译

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数据手册

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ASM3P2474AF-08SR 数据手册

October 2005

rev 1.0

ASM3P2474A

Low Power Peak EMI Reducing Solution

Features

The ASM3P2474A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented by using a proprietary all digital method.

Generates an EMI optimized clock signal at the

output.

Integrated loop filter components.

Operates with a 3.3V Supply.

Operating current less than 6mA.

Low power CMOS design.

Input frequency range : 13MHz to 30MHz

Generates a 1X and 2X low EMI spread spectrum

clock of the input frequency.

Output Frequency Selection through FSEL pin

Frequency deviation : -1.5% (Typ) @25MHz

: -1.5% (Typ) @50MHz

The ASM3P2474A modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

Applications

Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin

TSSOP packages.

The ASM3P2474A is targeted towards all portable

devices with very low power requirements like MP3

players and digital still cameras.

Product Description

The ASM3P2474A is

a versatile spread spectrum

Key Specifications

frequency modulator designed specifically for a wide

range of clock frequencies. The ASM3P2474A reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. The ASM3P2474A allows significant

system cost savings by reducing the number of circuit

board layers, ferrite beads and shielding that are

traditionally required to pass EMI regulations.

Description

Supply voltages

Cycle-to-Cycle Jitter

Output Duty Cycle

Modulation Rate Equation

Specification

VDD = 3.3V ± 0.3V

200pS (Typ)

45/55% (worst case)

F_IN/640

FSEL=0 -1.5% (Typ) @ 50MHz

FSEL=1 -1.5% (Typ) @ 25MHz

Frequency

Deviation

FSEL

VDD

Block Diagram

PLL

Modulation

XIN/CLKIN

XOUT

Crystal

Frequency

Divider

Oscillator

Output

VCO

Phase

Loop

Filter

Divider

Detector

Feedback

Divider

ModOUT

VSS

Alliance Semiconductor

2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...10

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与ASM3P2474AF-08SR相关器件

型号	品牌	获取价格	描述	数据表
ASM3P2474AF-08ST	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AF-08ST	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AF-08TR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AF-08TR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AF-08TT	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AF-08TT	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AG-06OR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AG-06OR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AG-08SR	ALSC	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2474AG-08SR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution

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