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ASM3I2508SPF-08ST

更新时间： 2024-11-07 20:29:19
品牌 Logo 应用领域
PULSECORE 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
7页 303K
描述
Clock Generator, 33.33MHz, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8

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ASM3I2508SPF-08ST 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：0.150 INCH, LEAD FREE, SOIC-8Reach Compliance Code：unknown
风险等级：5.77Is Samacsys：N
JESD-30 代码：R-PDSO-G8长度：4.9 mm
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C最大输出时钟频率：33.33 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED主时钟/晶体标称频率：25 MHz
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.91 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

ASM3I2508SPF-08ST 数据手册

 浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第2页浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第3页浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第4页浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第5页浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第6页浏览型号ASM3I2508SPF-08ST的Datasheet PDF文件第7页 
February 2005  
rev 0.4  
ASM3P2508SP  
Clock Synthesizer and Frequency Generator with Peak EMI reduction  
Features  
The ASM3P2508SP uses the most efficient and  
optimized modulation profile approved by the FCC.  
ASM3P2508SP modulates the output of a PLL in order to  
“spread” the bandwidth of a synthesized clock, and more  
importantly, decreases the peak amplitudes of its  
harmonics. This results in a significantly lower system  
EMI compared to the typical narrow band signal produced  
by oscillators and most frequency generators. Lowering  
EMI by increasing a signal’s bandwidth is called ‘spread  
spectrum clock generation’ (SSCG).  
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Dual PLL based Architecture  
Operates with a 3.3V ±0.3V supply.  
Generates an EMI optimized Spread Spectrum  
PCI Clock output  
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Generates a high accuracy non Spread T1 clock of  
±25ppm accuracy.  
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Generates a non spread system reference clock  
Low power CMOS design.  
Input frequency: 25 MHz.  
Outputs:  
In addition to the SSCG output, ASM3P2508SP  
generates two high accuracy clock signals -  
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a  
20MHz Sys_ REF_CLK.  
Sys_ REF_CLK: 20 MHz  
T1 Clock: 25 MHz (±25 ppm)  
PCI_CLK: 33.33MHz Spread Spectrum  
Frequency deviation: -0.5% (Typ).  
Available in 8L SOIC Package.  
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Applications  
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The ASM3P2508SP is targeted towards Consumer,  
Industrial, Data and Telecommunications applications.  
Product Description  
The ASM3P2508SP is a versatile Dual PLL based Clock  
Synthesizer and Frequency Generator optimised and  
designed specifically for three clock frequencies. The  
Key Specifications  
Description  
Supply voltages  
Input Frequency  
Cycle-to-Cycle Jitter  
Output Duty Cycle  
Output Rise and Fall Time  
SSC Modulation Rate  
SSC Frequency Deviation  
Specification  
VDD = 3.3V ±0.3V  
25 MHz  
175 pS ( Max)  
45/55%  
1.1 nS (Max)  
30KHz (Typ)  
-0.5% (Typ)  
PCI_CLK  
output  
from  
ASM3P2508SP  
reduces  
electromagnetic interference (EMI) at the clock source,  
allowing system wide reduction of EMI of all clock  
dependent signals. ASM3P2508SP allows significant  
system cost savings by reducing the number of circuit  
board layers, ferrite beads  
traditionally required to pass EMI regulations.  
&
shielding that are  
Block Diagram  
PWRDNB  
VDD  
Output  
Divider  
T1_CLK  
Input  
PLL 1  
Sys_REF_CLK  
Divider  
XIN/CLKIN  
XOUT  
Osc  
PCI_CLK  
PLL 2  
Output  
Divider  
Modulation  
VSS  
Alliance Semiconductor  
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com  
Notice: The information in this document is subject to change without notice.  
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