November 2003
rev 1.0
ASM3P2531A
Features
dependent signals. It allows significant system cost
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FCC approved method of EMI attenuation.
savings by reducing the number of circuit board layers
and shielding traditionally required to pass EMI
regulations.
Generates a low EMI spread spectrum of the
input clock frequency.
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Optimized for input frequency range between
35MHz – 55MHz.
The ASM3P2531A modulates the output of a single PLL
in order to spread the bandwidth of a synthesized clock,
thereby decreasing the peak amplitudes of its harmonics.
This results in significantly lower system EMI compared
to the typical narrow band signal produced by oscillators
and most clock generators. Lowering EMI by increasing
a signal’s bandwidth is called spread spectrum clock
generation.
Internal loop filter minimizes external
components and board space.
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Frequency Deviation: ±1.65%.
Low inherent cycle-to-cycle jitter.
3.3 V or 5 V operating voltage.
CMOS/TTL compatible inputs and outputs.
Ultra low power CMOS design: 5.50 mA @3.3 V.
Supports notebook VGA and other LCD timing
controller applications.
The ASM3P2531A uses the most efficient and optimized
modulation profile approved by the FCC and is
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Available in 8-pin SOIC and TSSOP.
implemented by using a proprietary all-digital method.
Product Description
The ASM3P2531A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. It reduces electromagnetic
interference (EMI) at the clock source allowing system-
wide reduction of EMI of downstream clock and data
Applications
The ASM3P2531A is targeted toward the notebook VGA
chip and other displays using an LVDS interface, PC
peripheral devices, and embedded systems
Block Diagram
STOP
VDD
PLL
Modulation
CLKIN
Crystal
Oscillator
Frequency
Divider
Output
Divider
Phase
Detector
Loop
Filter
VCO
Feedback
Divider
MODOUT
VSS
Low Frequency EMI Reduction
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Notice: The information in this document is subject to change without notice.