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AS7C34096-20JC PDF预览

AS7C34096-20JC

更新时间: 2024-10-27 22:56:35
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
9页 247K
描述
5V/3.3V 512K X8 CMOS SRAM

AS7C34096-20JC 数据手册

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AS7C4096  
AS7C34096  
®
AC test conditions  
- Output load: see Figure B or Figure C.  
Thevenin equivalent:  
168  
- Input pulse level: GND to 3.0V. See Figures A, B, and C.  
- Input rise and fall times: 2 ns. See Figure A.  
- Input and output timing reference levels: 1.5V.  
DOUT  
+1.728V  
+3.3V  
+5V  
480  
320  
+3.0V  
GND  
DOUT  
255  
DOUT  
350Ω  
90%  
10%  
90%  
10%  
C13  
C13  
2 ns  
Figure A: Input pulse  
GND  
GND  
Figure C: 3.3V Output load  
Figure B: 5V Output load  
Notes  
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.  
This parameter is sampled, but not 100% tested.  
For test conditions, see AC Test Conditions.  
t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.  
This parameter is guaranteed, but not tested.  
WE is HIGH for read cycle.  
CE and OE are LOW for read cycle.  
Address valid prior to or coincident with CE transition Low.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 Not applicable.  
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.  
1/13/05; v.1.9  
Alliance Semiconductor  
P. 6 of 9  

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