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AS7C3364NTD32B-133TQI PDF预览

AS7C3364NTD32B-133TQI

更新时间: 2024-11-17 22:16:27
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器
页数 文件大小 规格书
19页 437K
描述
3.3V 64K x 32/36 Pipelined SRAM with NTD

AS7C3364NTD32B-133TQI 数据手册

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April 2005  
AS7C3364NTD32B  
AS7C3364NTD36B  
®
3.3V 64K×32/36 Pipelined SRAM with NTDTM  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Organization: 65,536 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.0/3.5/4.0 ns  
• Fast OE access time: 3.0/3.5/4.0 ns  
• Fully synchronous operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Byte write enables  
• Interleaved or linear burst modes  
• Snooze mode for reduced power standby  
Logic block diagram  
16  
16  
Q
DAddress  
register  
Burst logic  
A[15:0]  
16  
16  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
16  
addr. registers  
CLK  
R/W  
BWa  
BWb  
BWc  
BWd  
Control  
logic  
CLK  
ADV / LD  
128K x 32/36  
SRAM  
Array  
LBO  
ZZ  
CLK  
32/36  
32/36  
Data  
DQ [a:d]  
Q
D
Input  
Register  
CLK  
32/36  
32/36  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ [a:d]  
Selection Guide  
-200  
-166  
6
-133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
5
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.0  
375  
135  
30  
166  
3.5  
350  
120  
30  
MHz  
ns  
325  
110  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
4/28/05; v.1.3  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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