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AS7C33512NTF18A-65TQC PDF预览

AS7C33512NTF18A-65TQC

更新时间: 2024-11-24 15:27:59
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
14页 307K
描述
ZBT SRAM, 512KX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQPF-100

AS7C33512NTF18A-65TQC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.52
最长访问时间:6.5 nsJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:9437184 bit内存集成电路类型:ZBT SRAM
内存宽度:18功能数量:1
端子数量:100字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX18封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AS7C33512NTF18A-65TQC 数据手册

 浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第2页浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第3页浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第4页浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第5页浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第6页浏览型号AS7C33512NTF18A-65TQC的Datasheet PDF文件第7页 
AS7C33512NTF18A  
July 2004  
®
3.3V 512K×18 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Organization: 524,288 words × 18 bits  
• NTD™1 architecture for efficient bus operation  
• Fast clock to data access: 6.5/7.5 ns  
• Fast OE access time: 3.5 ns  
• Available in 100-pin TQFP  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3 core power supply  
• Fully synchronous operation  
• Flow-through mode  
• Asynchronous output enable control  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• 30 mW typical standby power  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
1. NTD is a trademark of Alliance Semiconductor Corporation. All  
trademarks mentioned in this document are the property of their respective  
owners.  
Logic Block Diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
BWb  
Control  
logic  
CLK  
ADV / LD  
FT  
512K x 18  
SRAM  
array  
LBO  
ZZ  
CLK  
18  
18  
DQ [a,b]  
Data  
input  
register  
D
Q
18  
18  
CLK  
18  
CLK  
CEN  
Output  
buffer  
OE  
18  
OE  
DQ [a,b]  
Selection Guide  
–65  
7.5  
6.5  
250  
120  
30  
-75  
8.5  
7.5  
225  
100  
30  
Units  
ns  
Minimum cycle time  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
ns  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
7/12/04, v. 1.0  
Alliance Semiconductor  
P. 1 of 14  
Copyright © Alliance Semiconductor. All rights reserved.  

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