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AS7C33512NTF32A-75TQC PDF预览

AS7C33512NTF32A-75TQC

更新时间: 2024-11-26 23:00:35
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
18页 426K
描述
3.3V 512K x 32/36 Flowthrough Synchronous SRAM with NTD

AS7C33512NTF32A-75TQC 数据手册

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April 2005  
AS7C33512NTF32A  
AS7C33512NTF36A  
®
3.3V 512K × 32/36 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Organization: 524,288 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
• Fast clock to data access: 7.5/8.5/10 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
DDQ  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Individual byte write and global write  
Logic block diagram  
19  
19  
A[18:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
19  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
512K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
Output  
Buffer  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-75  
-85  
10  
-10  
12  
Units  
Minimum cycle time  
8.5  
7.5  
275  
90  
ns  
ns  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.5  
250  
80  
10  
230  
80  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
60  
60  
60  
4/21/05, v 1.3  
Alliance Semiconductor  
P. 1 of 18  
Copyright © Alliance Semiconductor. All rights reserved.  

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