AS7C33256PFS32A
AS7C33256PFS36A
®
Functional description
The AS7C33256PFS32A and AS7C33256PFS36A are high-performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given
technology.
Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
1
(TMS320C6X), and PowerPC™ -based systems in computing, datacomm, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.6/7.5/10 ns with clock access times (t ) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
CD
Two-chip enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst operation is initiated in one of two
ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed
by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High.
Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With
LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn
is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to
the next burst address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33256PFS32A and AS7C33256PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate
at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package and in a 119-pin 14 × 20 mm BGA package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Signals
Address and control pins
I/O pins
Test conditions
VIN = 0V
Max
5
Unit
pF
CI/O
VIN = VOUT = 0V
7
pF
Write enable truth table (per byte)
GWE
BWE
BWn
WEn
T
L
X
L
X
L
H
T
H
H
L
X
H
F*
F*
H
ꢀꢁꢂꢃꢄX = Don’t Care, L = Low, H = High, T = True, F = False; *= Valid read; n = a, b, c, d; WE, WEn = internal write signal.
Burst order table
Interleaved Burst Order
Linear Burst Order
LBO=0
LBO=1
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address 00
First increment 01
Second increment 10
Third increment 11
01
10
11
00
10
11
00
01
11
00
01
10
™
1 PowerPC is a trademark International Business Machines Corporation.
4/15/02; v.1.9
Alliance Semiconductor
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