April 2002
Preliminary
AS7C33256PFS32A
AS7C33256PFS36A
®
3.3V 256K × 32/36 pipeline burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” option
• Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD32A/
AS7C33256PFD36A)
• Pentium®1compatible architecture and timing
• Asynchronous output enable control
• Available in100-pin TQFP and 119-pin BGA packages
• Byte write enables
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• NTD™1 pipeline architecture available
(AS7C33256NTD32A/ AS7C33256NTD36A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33256PFS32A2 or AS7C33256PFS36A2
®
1 Pentium is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective
owners.
Logic block diagram
LBO
Q0
Burst logic
Q1
CLK
ADV
ADSC
CLK
CE
CLR
256K × 32/36
Memory
ADSP
18
16
18
18
array
D
CE
CLK
Q
A[17:0]
Address
register
36/32
36/32
BWE
GWE
d
D
Q
Q
Q
Q
DQ
d
Byte write
BW
registers
CLK
D
DQ
c
BW
c
Byte write
registers
CLK
D
DQ
b
BW
b
Byte write
registers
CLK
D
DQ
a
4
BW
a
Byte write
registers
CLK
D
CE0
CE1
CE2
OE
Output
registers
CLK
Q
Q
Input
registers
CLK
Enable
register
CE
CLK
D
Enable
delay
Power
down
ZZ
register
CLK
36/32
DQ[a:d]
OE
FT
Selection guide
–166
–150
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
6
6.6
150
3.8
450
110
30
Maximum pipelined clock frequency
166
3.5
475
130
30
100
5
MHz
ns
Maximum pipelined clock access time
Maximum operating current
425
100
30
325
90
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
4/15/02; v.1.9
Alliance Semiconductor
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