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AS7C33256PFS36A PDF预览

AS7C33256PFS36A

更新时间: 2022-12-04 00:29:18
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
20页 528K
描述
3.3V 256K x 32/36 pipelined burst synchronous SRAM

AS7C33256PFS36A 数据手册

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November 2004  
AS7C33256PFS32A  
AS7C33256PFS36A  
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM  
Features  
• Organization: 262,144 words x 32 or 36 bits  
• Fast clock speeds to 166 MHz  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• Fast clock to data access: 3.5/4.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous register-to-register operation  
• Single-cycle deselect  
• 2.5V or 3.3V I/O operation with separate V  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
• Common data inputs and data outputs  
DDQ  
• Asynchronous output enable control  
• Available in100-pin TQFP  
• 30 mW typical standby power in power down mode  
• Individual byte write and global write  
Logic block diagram  
LBO  
CLK  
CLK  
CE  
ADV  
Burst logic  
ADSC  
CLR  
256K × 32/36  
Memory  
array  
18  
ADSP  
2
2
18  
16  
18  
D
Q
A
[17:0]  
Address  
CE  
CLK  
register  
36/32  
36/32  
BWE  
GWE  
d
D
Q
DQ  
d
Byte write  
BW  
registers  
CLK  
D
Q
DQ  
c
BW  
c
Byte write  
registers  
CLK  
D
Q
DQ  
b
BW  
b
Byte write  
registers  
CLK  
D
Q
DQ  
a
4
BW  
a
Byte write  
registers  
CLK  
D
CE0  
CE1  
CE2  
OE  
Q
Q
Output  
Input  
Enable  
register  
registers  
registers  
CE  
CLK  
CLK  
CLK  
D
Enable  
Power  
down  
delay  
ZZ  
register  
CLK  
36/32  
DQ[a:d]  
OE  
Selection guide  
–166  
6
–133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
166  
3.5  
475  
130  
30  
MHz  
ns  
425  
100  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
11/30/04, v.3.1  
Alliance Semiconductor  
P. 1 of 20  
Copyright ©Alliance Semiconductor. All rights reserved.  

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