Datasheet > 存储 > SRAM> AS7C33256PFS32A-133TQI

AS7C33256PFS32A-133TQI

更新时间： 2024-01-06 02:14:40

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器
页数	文件大小	规格书
20页	528K
描述
3.3V 256K x 32/36 pipelined burst synchronous SRAM

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技术参数
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AS7C33256PFS32A-133TQI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.35	最长访问时间：	10 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e3	长度：	20 mm
内存密度：	8388608 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	32	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	245	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

AS7C33256PFS32A-133TQI 数据手册

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AS7C33256PFS32A

AS7C33256PFS36A

Functional description

The AS7C33256PFS32A and AS7C33256PFS36A are high-performance CMOS 8-Mbit Synchronous Static Random Access

Memory (SRAM) devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline

for highest frequency on any given technology.

Fast cycle times of 6/7.5 ns with clock access times (t ) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Two-chip

enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst operation is initiated in one of

two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV)

allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.

In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled LOW, and both address strobes are HIGH. Burst mode is selectable with the LBO

input. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the

device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in

single cycle deselect features during real cycle.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

• Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C33256PFS32A and AS7C33256PFS36A family operates from a core 3.3V power supply. I/Os use a separate power

supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

TQFP thermal Capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

Test conditions

= 0V

Min

Max

Unit

= V = 0V

OUT

I/O

Guaranteed not tested

TQFP thermal resistance

Description

Conditions

Symbol

Typical

Units

°C/W

1–layer

4–layer

θ_JA

Thermal resistance

(junction to ambient)¹

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

Thermal resistance

(junction to top of case)¹

θ_JC

°C/W

1 This parameter is sampled

11/30/04, v.3.1

Alliance Semiconductor

P. 4 of 20

1 2 345 6 7...20

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与AS7C33256PFS32A-133TQI相关器件

型号	品牌	描述	获取价格	数据表
AS7C33256PFS32A-133TQIN	ALSC	3.3V 256K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33256PFS32A-150BC	ISSI	Standard SRAM, 256KX32, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS32A-150BI	ISSI	Standard SRAM, 256KX32, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS32A-166BC	ISSI	Standard SRAM, 256KX32, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS32A-166BI	ISSI	Standard SRAM, 256KX32, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS32A-166TQC	ALSC	3.3V 256K x 32/36 pipelined burst synchronous SRAM	获取价格

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