Datasheet > AS7C33256PFS32A-150BI

AS7C33256PFS32A-150BI

更新时间： 2022-12-01 20:08:25

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
14页	384K
描述
Standard SRAM, 256KX32, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

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April 2002

Preliminary

AS7C33256PFS32A

AS7C33256PFS36A

3.3V 256K × 32/36 pipeline burst synchronous SRAM

Features

• Organization: 262,144 words x 32 or 36 bits

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

• Fast OE access time: 3.5/3.8/4.0/5.0 ns

• Fully synchronous register-to-register operation

• Single register “Flow-through” option

• Single-cycle deselect

- Dual-cycle deselect also available (AS7C33256PFD32A/

AS7C33256PFD36A)

• Pentium®¹compatible architecture and timing

• Asynchronous output enable control

• Available in100-pin TQFP and 119-pin BGA packages

• Byte write enables

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V_DDQ

• 30 mW typical standby power in power down mode

• NTD™¹pipeline architecture available

(AS7C33256NTD32A/ AS7C33256NTD36A)

• Available in both 2 chip enable and 3 chip enable

- 2 CE part number is AS7C33256PFS32A2 or AS7C33256PFS36A2

1 Pentium is a registered trademark of Intel Corporation. NTD™ is a

trademark of Alliance Semiconductor Corporation. All trademarks

mentioned in this document are the property of their respective

owners.

Logic block diagram

LBO

Burst logic

CLK

ADV

ADSC

CLK

CLR

256K × 32/36

Memory

ADSP

array

CLK

A[17:0]

Address

36/32

BWE

GWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Enable

CLK

Enable

delay

Power

down

CLK

36/32

DQ[a:d]

Selection guide

–166

–150

–133

7.5

133

–100

Units

Minimum cycle time

6.6

150

3.8

450

110

Maximum pipelined clock frequency

166

3.5

475

130

100

MHz

Maximum pipelined clock access time

Maximum operating current

425

100

325

Maximum standby current

Maximum CMOS standby current (DC)

4/15/02; v.1.9

Alliance Semiconductor

P. 1 of 14

12 3 4 5 6 7...14

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