Datasheet > AS4LC4M4E0

AS4LC4M4E0

更新时间： 2022-01-22 08:55:00

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
15页	266K
描述
4M x 4 CMOS DRAM (EDO) Family

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数据手册

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AS4LC4M4E0 数据手册

AS4LC4M4E0

AS4LC4M4E1

Notes

, I , I , and I

are dependent on frequency.

CC6

CC1 CC3 CC4

and I

depend on output loading. Specified values are obtained with the output open.

CC4

CC1

An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal

refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

extended periods of bias without clocks (greater than 8 ms).

AC Characteristics assume t = 2 ns. All AC parameters are as described in AC test conditions below

(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .

Operation within the t

(max) limit insures that t

(max) can be met. t

(max) is specified as a reference point only. If t

is greater than the

RCD

RAC

RCD

specified t

(max) limit, then access time is controlled exclusively by t

RCD

CAC

Operation within the t

(max) limit insures that t

(max) can be met. t

(max) is specified as a reference point only. If t

is greater than the

RAD

RAC

RAD

specified t

(max) limit, then access time is controlled exclusively by t .

RAD

Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).

Either t or t must be satisfied for a read cycle.

RCH

RRH

(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t

is referenced from

OFF

rising edge of RAS or CAS, whichever occurs last.

t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.

WCS WCH RWD CWD

AWD

If t_WS≥ t (min) and t_WH≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the

cycle. If t_RWD≥ t

(min), t

≥ t

(min) and t_AWD≥ t

(min), the cycle is a read-write cycle and the data out will contain data read from the

RWD

CWD

AWD

selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.

13 Access time is determined by the longest of t or t or t

CAA

CAC

CPA

_ASC≥ t to achieve t (min) and t

(max) values.

CPA

15 These parameters are sampled and not 100% tested.

AC test conditions

- Access times are measured with output reference levels of V

2.4V and V = 0.4V,

= 2.0V and V = 0.8V

- Input rise and fall times: 2 ns

+3.3V

R1 = 828Ω

D_out

50 pF*

R2 = 295Ω

*including scope

and jig capacitance

GND

Figure B: Equivalent output load

(AS4LC4M4E0)

(AS4LC4M4E1)

4/11/01; V.1.1

Alliance Semiconductor

P. 8 of 15

1...5 6 789 10 11...15

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与AS4LC4M4E0相关器件

型号	品牌	描述	获取价格	数据表
AS4LC4M4E0-45JC	ALSC	EDO DRAM, 4MX4, 45ns, CMOS, PDSO24	获取价格
AS4LC4M4E0-45TC	ALSC	EDO DRAM, 4MX4, 45ns, CMOS, PDSO24	获取价格
AS4LC4M4E0-50JC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-50JI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-50TC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-50TI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-60JC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-60JI	ALSC	EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24	获取价格
AS4LC4M4E0-60TC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-60TI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E0-70JC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1	ETC	4M x 4 CMOS DRAM (EDO) Family	获取价格
AS4LC4M4E1-50JC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-50JI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-50TC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-50TI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-60JC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-60JI	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-60TC	ETC	x4 EDO Page Mode DRAM	获取价格
AS4LC4M4E1-60TI	ETC	x4 EDO Page Mode DRAM	获取价格

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