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AS4DDR264M72PBG1R-38/ET PDF预览

AS4DDR264M72PBG1R-38/ET

更新时间: 2024-11-11 06:37:51
品牌 Logo 应用领域
AUSTIN 内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
28页 366K
描述
64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit

AS4DDR264M72PBG1R-38/ET 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:208
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.68
Is Samacsys:N访问模式:MULTI BANK PAGE BURST
最长访问时间:0.5 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B208长度:23 mm
内存密度:4831838208 bit内存集成电路类型:DDR DRAM
内存宽度:72功能数量:1
端口数量:1端子数量:208
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:64MX72
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:3.65 mm
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:16 mmBase Number Matches:1

AS4DDR264M72PBG1R-38/ET 数据手册

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iPEM  
4.8 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M72PBG1  
64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS  
iNTEGRATED Plastic Encapsulated Microcircuit  
FEATURES  
BENEFITS  
„
„
„
DDR2 Data rate = 667, 533, 400  
„
„
61% Space Savings  
Available in Industrial, Enhanced and Military Temp  
Package:  
55% I/O reduction vs Individual package  
approach  
Proprietary Enchanced Die Stacked iPEM  
208 Plastic Ball Grid Array (PBGA), 16 x 23mm  
1.00mm ball pitch  
„
„
Reduced part count  
Reduced trace lengths for lower parasitic  
capacitance  
„
„
„
„
Differential data strobe (DQS, DQS#) per byte  
Internal, pipelined, double data rate architecture  
4n-bit prefetch architecture  
„
„
„
Suitable for hi-reliability applications  
Upgradable to 128M x 72 density in future  
Pin/Function equivalent to White  
W3H64M72E-xBSx  
DLL for alignment of DQ and DQS transitions with  
clock signal  
Eight internal banks for concurrent operation  
(Per DDR2 SDRAM Die)  
„
ConfigurationAddressing  
„
„
„
„
„
„
„
„
„
„
Programmable Burst lengths: 4 or 8  
Auto Refresh and Self Refresh Modes (I/T Version)  
On Die Termination (ODT)  
Parameter  
64Megx72  
8Megx16x8Banks  
8K  
Configuration  
RefreshCount  
RowAddress  
BankAddress  
ColumnAddress  
Adjustable data – output drive strength  
1.8V 0.1V common core power and I/O supply  
Programmable CAS latency: 3, 4, 5, 6 or 7  
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5  
Write latency = Read latency - 1* tCK  
Organized as 64M x 72  
A0ͲA12(8k)  
BA0ͲBA2(8)  
A0ͲA9(1K)  
Weight: AS4DDR264M72PBG1 ~ 2.0 grams typical  
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only  
FUNCTIONAL BLOCK DIAGRAM  
Ax, BA0-2  
ODT  
VRef  
VCC  
VCC
VCC
VCC
VCC
VCC
VSS  
VSSQ  
VCCL  
VSSDL  
VSSQ  
VCCL  
VSSDL  
VSSQ  
VCCL  
VSSQ  
VCCL  
VSSQ  
VCCL  
VSSQ  
VSSDL  
VSSDL  
VSSDL  
D
A
B
C
DQ64-71  
CS\  
WE\  
RAS\  
CAS\  
CKE\  
2
2
2
2
2
2
ODT  
ODT  
2
2
2
LDM4  
UDMx, LDMx  
UDSQx,UDSQx\  
LDSQx, LDSQx\  
CKx,CKx\  
2
2
2
2
2
2
2
2
2
2
UDM4  
C
B
D
DQ32-47  
DQ16-31  
A
DQ0-15  
DQ48-63  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M72PBG1  
Rev. 3.0 6/09  
1

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