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AS4DDR264M72PBG-5/XT PDF预览

AS4DDR264M72PBG-5/XT

更新时间: 2024-02-21 20:23:46
品牌 Logo 应用领域
AUSTIN 内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
28页 257K
描述
64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

AS4DDR264M72PBG-5/XT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:BGA, BGA255,16X16,50针数:255
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.4
Is Samacsys:N访问模式:MULTI BANK PAGE BURST
最长访问时间:0.6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
交错的突发长度:4,8JESD-30 代码:R-PBGA-B255
JESD-609代码:e0长度:32 mm
内存密度:4831838208 bit内存集成电路类型:DDR DRAM
内存宽度:72功能数量:1
端口数量:1端子数量:255
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:64MX72
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA255,16X16,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES连续突发长度:4,8
最大待机电流:0.035 A子类别:DRAMs
最大压摆率:1.3 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:25 mmBase Number Matches:1

AS4DDR264M72PBG-5/XT 数据手册

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iPEM  
4.8 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR264M72PBG  
64Mx72 DDR2 SDRAM  
iNTEGRATED Plastic Encapsulated Microcircuit  
BENEFITS  
FEATURES  
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„
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DDR2 Data rate = 667, 533, 400  
„
SPACE conscious PBGA defined for easy  
SMT manufacturability (50 mil ball pitch)  
Reduced part count  
47% I/O reduction vs Individual CSP approach  
Reduced trace lengths for lower parasitic  
capacitance  
Available in Industrial, Enhanced and Extended Temp  
Package:  
„
„
„
255 Plastic Ball Grid Array (PBGA), 25 x 32mm  
1.27mm pitch  
Differential data strobe (DQS, DQS#) per byte  
Internal, pipelined, double data rate architecture  
4n-bit prefetch architecture  
DLL for alignment of DQ and DQS transitions with  
clock signal  
„
„
„
„
„
„
Suitable for hi-reliability applications  
Upgradable to 128M x 72 density in future  
„
Eightinternal banks for concurrent operation  
(Per DDR2 SDRAM Die)  
„
„
„
„
„
„
„
„
„
„
Programmable Burst lengths: 4 or 8  
Auto Refresh and Self Refresh Modes (I/T Version)  
On Die Termination (ODT)  
Adjustable data – output drive strength  
1.8V ±0.1V power supply and I/O (VCC/VCCQ)  
Programmable CAS latency: 3, 4, 5, 6 or 7  
Posted CAS additive latency: 0, 1, 2, 3, 4 or 5  
Write latency = Read latency - 1* tCK  
Organized as 64M x 72 w/ support for x80  
Weight: AS4DDR264M72PBG ~ 3.5 grams typical  
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only  
FUNCTIONAL BLOCK DIAGRAM  
2
Ax, BA0-1  
ODT  
VRef  
VCC  
VCCQ  
VSS  
VSSQ  
VCCL  
VCCL  
VCCL  
VCCL  
VCCL  
VSSDL  
VSSDL  
VSSDL  
VSSDL  
VSSDL  
A
B
C
D
2
2
2
2
2
2
2
2
DQ64-79  
CS0\  
CS1\  
CS2\  
CS3\  
2
2
2
2
2
3
3
3
3
2
3
3
3
3
CS4\  
2
UDMx, LDMx  
UDSQx,UDSQx\  
LDSQx, LDSQx\  
RASx\,CASx\,WEx\  
CKx,CKx\,CKEx  
3
3
C
B
D
DQ16-31  
A
DQ0-15  
DQ32-47  
DQ48-63  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR264M72PBG  
Rev. 1.5 11/07  
1

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