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AS4C1M16F5-50TI PDF预览

AS4C1M16F5-50TI

更新时间： 2024-01-11 17:16:40
品牌 Logo 应用领域
其他 - ETC 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
21页 475K
描述
5V 1M X 16 CMOS DRAM

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AS4C1M16F5-50TI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSOP44/50,.46,32
针数：50Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.78Is Samacsys：N
访问模式：FAST PAGE最长访问时间：50 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e0
长度：20.95 mm内存密度：16777216 bit
内存集成电路类型：FAST PAGE DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：44字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44/50,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE峰值回流温度（摄氏度）：240
电源：5 V认证状态：Not Qualified
刷新周期：1024座面最大高度：1.2 mm
自我刷新：NO最大待机电流：0.002 A
子类别：DRAMs最大压摆率：0.145 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

AS4C1M16F5-50TI 数据手册

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AS4C1M16F5  
®
Functional description  
The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as  
1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design  
techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The  
Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia  
and router switch applications.  
The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)  
can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column  
addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used  
to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The  
AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access.  
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:  
•
RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.  
• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.  
•
CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.  
Outputs are high-impedence (OE and WE are don't care).  
• Normal read or write cycles refresh the row being accessed.  
The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates  
with a single power supply of 5V 0.5V. The device provides TTL compatible inputs and outputs.  
Logic block diagram  
Data  
DQ  
buffers  
VCC  
Column decoder  
Sense amp  
DQ1 to DQ16  
GND  
RAS clock  
generator  
RAS  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
OE  
1024 × 1024 × 16  
Array  
CAS clock  
generator  
UCAS  
LCAS  
(16,777,216)  
Substrate bias  
generator  
WE clock  
generator  
WE  
Recommended operating conditions  
Parameter  
Symbol  
VCC  
Min  
4.5  
0.0  
2.4  
–0.5†  
0
Nominal  
Max  
5.5  
0.0  
VCC  
0.8  
70  
Unit  
V
AS4C1M16F5  
5.0  
0.0  
–
Supply voltage  
Input voltage  
GND  
VIH  
V
AS4C1M16F5  
V
VIL  
–
V
Commercial  
Industrial  
–
Ambient operating temperature  
TA  
°C  
-40  
–
85  
†
V
min -3.0V for pulse widths less than 5 ns.  
IL  
Recommended operating conditions apply throughout this document unlesss otherwise specified.  
4/11/01; v.0.9.1  
Alliance Semiconductor  
P. 2 of 21  
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