Datasheet > AS4C16M16MD1-6BCN

AS4C16M16MD1-6BCN

更新时间： 2024-01-24 22:46:38

品牌	Logo	应用领域
ALSC		动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
55页	6130K
描述
Programmable output buffer driver strength

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AS4C16M16MD1-6BCN 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	TFBGA,	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.24
Factory Lead Time：	8 weeks	风险等级：	1.69
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PBGA-B60
长度：	9 mm	内存密度：	268435456 bit
内存集成电路类型：	DDR DRAM	内存宽度：	16
湿度敏感等级：	3	功能数量：	1
端口数量：	1	端子数量：	60
字数：	16777216 words	字数代码：	16000000
工作模式：	SYNCHRONOUS	组织：	16MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.025 mm
自我刷新：	YES	最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.7 V	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8 mm
Base Number Matches：	1

AS4C16M16MD1-6BCN 数据手册

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S4C16M16MD1

256Mb MOBILE DDR SDRAM

3.1 Signal Descriptions

SIGNAL NAME TYPE

DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control

input signals are sampled on the crossing of the positive edge of CK

and negative edge of CK. Input and output data is referenced to the

crossing of CK and CK (both directions of crossing). Internal clock

signals are derived from CK/CK.

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal

clock signals, and device input buffers and output drivers. Taking CKE

LOW provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in

any bank). CKE is synchronous for all functions except for SELF

REFRESH EXIT, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE, are disabled during power-down and self

refresh mode which are contrived for low standby power consumption.

CK,/CK

CKE

Input

Chip Select: CS enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS is

registered HIGH. CS provides for external bank selection on systems

with multiple banks. CS is considered part of the command code.

/CS

Input Command Inputs: RAS, CAS and WE (along with CS) define the

command being entered.

/RAS,/CAS,/WE

Input Data Mask: DM is an input mask signal for write data. Input data is

masked when DM is sampled HIGH along with that input data during a

WRITE access. DM is sampled on both edges of DQS. Although DM pins

are input-only, the DM loading matches the DQ and DQS loading. For

Input

LDM,UDM

x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM

corresponds to the data on DQ8-DQ15.

Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,

READ, WRITE or PRECHARGE command is being applied.

Input Address Inputs: provide the row address for ACTIVE commands, and

the column address and AUTO PRECHARGE bit for READ / WRITE

commands, to select one location out of the memory array in the

respective bank. The address inputs also provide the opcode during a

MODE REGISTER SET command.

BA0,BA1

A [n : 0]

Data Bus: Input / Output

DQ0-DQ15

I/O

Data Strobe: Output with read data, input with write data. Edge-aligned

with read data, centered with write data. Used to capture write data.

LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to the

data on DQ8-DQ15.

I/O

LDQS,UDQS

No Connect: No internal electrical connection is presen

VDDQ

VSSQ

VDD

VSS

Supply

I/O Power Supply

I/O Ground

Power Supply

Ground

Table 1 — Signal Descriptions

Mar, 28, 2013

- 5 -

1 2 3 456 7 8...55

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与AS4C16M16MD1-6BCN相关器件

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AS4C16M16S-6BIN	ALSC	Programmable Mode registers	获取价格
AS4C16M16S-6TAN	ALSC	Programmable Mode registers	获取价格
AS4C16M16S-6TCN	ALSC	Programmable Mode registers	获取价格
AS4C16M16S-6TIN	ALSC	Programmable Mode registers	获取价格

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