Datasheet > AN2635

AN2635

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		闪存
页数	文件大小	规格书
36页	149K
描述
On-Chip FLASH Programming Routines

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数据手册

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AN2635 数据手册

On-Chip Routines Source Code

;*********************************************************************

;* Step 7 and Step 8 are repeated until a value in location LADDR+1

;* reaches to zero.

;*********************************************************************

PRGstep7:

pshx

pshh

;[2] temp flash pointer (lo) [F]

;[2] temp flash pointer (hi) [G]

;* Current stack frame

SP+1 [G] flash pointer (hi) temp store so H:X available

SP+2 [F] flash pointer (lo) temp store so H:X available

SP+3 [E] PCH (return addr hi)

SP+4 [D] PCL (return addr lo)

SP+5 [C] bytes remaining to prog..not counting this block

SP+6 [B] LADDR+1

SP+7 [A] LADDR

clrh

ldx

lda

pulh

pulx

sta

;[1] clear upper half of H:X

RamPntrLo

DATA,x

;[3] get DATA array pointer (lo)

;[3] read data from a DATA array

;[2] restore flash pointer (hi) [G]

;[2] restore flash pointer (lo) [F]

;[.w] write data to Flash addr

;

(Prog Algo Step 7)

;*********************************************************************

;* Compute Tprog based on bus speed

;* For slowest bus speeds (CPUSPD=4), Tprog = 38 bus cycles. For

;* other speeds, Tprog = 8 * CPUSPD + 5 bus cycles.

PRGstep8:

;delay for Tprog (Prog Algo Step 8)

;[3]

;[2] if CPUSPD=4 (bus = 1MHz),

;[3] Tprog=38 cycles

;[1] for other cases

lda

cmp

beq

asla

sub

CPUSPD

PRGstep9

;[2] A = 2 x CPUSPD - 9

DelayPRG:

PRGstep9:

nop

;[1] 1~ delay

;[3] Tprog = 8 * CPUSPD + 5 cycles

dbnza DelayPRG

;

(Prog Algo Step 9)

aix

inc

dec

bne

;[2] point to next FLASH address

;[4] increment DATA array pointer

;[4] decrement byte counter

RamPntrLo

ByteCntr

PRGstep7

;[3] loop until byte counter is = 0

rol

ror

sei

1,sp

;[5] ROL/ROR/SEI makes 12~ delay

;[5] to match delay to PRGstep10

;[2]

PRGstep10:

PRGstep11:

PRGstep12:

lda

sta

#mHVEN

FLCR

;[2] clear PGM, leave HVEN=1

;[..w.]

(Prog Algo Step 10)

lda

dbnza

CPUSPD

;[3] delay for time Tnvh

;[3*CPUSPD]

(Prog Algo Step 11)

clra

sta

;[1] pattern to clear HVEN

;[..w.] clear HVEN bit in FLCR

FLCR

On-Chip FLASH Programming Routines, Rev. 4

Freescale Semiconductor

1...29 30 313233 34 35 36

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