AMIS-70020

更新时间： 2024-01-22 02:56:01

品牌	Logo	应用领域
AMI		计数器电源电路电源管理电路光电二极管
页数	文件大小	规格书
7页	331K
描述
Power Failure Elapsed Time Counter

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技术参数
数据手册

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AMIS-70020 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	0.150 INCH, SO-8	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.18
Is Samacsys：	N	可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT	JESD-30 代码：	R-PDSO-G8
长度：	4.9 mm	信道数量：	1
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-10 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	座面最大高度：	1.72 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	3.9 mm	Base Number Matches：	1

AMIS-70020 数据手册

AMIS-70020 Power Failure Elapsed Time Counter

Data Sheet

Absolute Maximum Ratings

Stresses above those listed in this clause may cause

immediate and permanent device failure. It is not implied

that more than one of these conditions can be applied

simultaneously.

Symbol

VCC

VDDmr

Tamb,mr

Tj,mr

Description

Min

-0.3

-10

Max

150

Unit

°C

Power supply voltage

Ambient temperature under bias

Junction temperature

Digital input levels

VIH

VDD + 0.3

VIL

VDD – 0.3

Electrical Overstress Immunity

Electrostatic discharges on component level:

Latch-up immunity:

(1) The device withstands 2000V Human Body Model ESD

pulses when tested according to MIL STD 883 method

3015.5 (pin combination 2).

(2) Static latch-up protection level is 100mA at 25°C when

tested according to EIA/JESD78.

8.0 Detailed Electrical and Functional Description

Digital Interface

The digital interface with a microcontroller can be made by

means of only two digital connections. The first is the clock

signal to be applied to the AMIS-70020 UC_CLK pin and

the second is the data line to be read by the microcontroller

from the Q_OUT pin. After a POR or after a power failure

(CUT_OFF) the 15 bit shift register is loaded with the

counter value and connected to the Q_OUT pin. The most

significant bit, MSB is already present and can be read at

the Q_OUT pin. Applying clocks at a maximum rate of

10MHz on UC_CLK will shift out the remaining counter bits.

After the fifteenth clock, the internal oscillator frequency

will be connected to the Q_OUT pin as a running clock

signal. By measuring the period of this signal, the time a

cut-off was present can be calculated by the

microcontroller.

An internal pull down resistor is connected to the pin

Q_OUT, in order to avoid the parasitic shift of the counting

If VCC is powered up, a third optional pin – CLK - gives the

counter clock signal of about 1Hz. This clock is the internal

oscillator, divided by 1024 and can also be used to calibrate

the application.

Connections made with the microcontroller are separated

by level shifters. When in power failure mode, the inputs of

the AMIS-70020 are fixed to zero state. This will prevent

unwanted current leaking.

AMI Semiconductor

www.amis.com

1 2 345 6 7

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