ADVANCE INFORMATION
Am54BDS128AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
■ Power dissipation (typical values, CL = 30 pF)
MCP Features
■ Power supply voltage of 1.65 to 1.95 volt
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
■ High performance
— Program/Erase: 15 mA
— Access time as fast as 70 ns/ 54 Mhz Burst
— Standby mode: 0.4 µA
■ Package
Hardware features
— 93-Ball FBGA
■ Software command sector locking
■ Operating Temperature
— –40°C to +85°C
■ Handshaking: host monitors operations via RDY
output
Flash Memory Features
■ Hardware reset input (RESET#)
■ WP# input
ARCHITECTURAL ADVANTAGES
— Write protect (WP#) function protects sectors 0, 1
(bottom boot) or sectors 132 and 133 (top boot),
regardless of sector protect status
■ Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
■ Manufactured on 0.17 µm process technology
■ Simultaneous Read/Write operation
■ ACC input: Acceleration function reduces
programming time; all sectors locked when ACC = VIL
— Data can be continuously read from one bank while
executing erase/program functions in other bank
■ CMOS compatible inputs, CMOS compatible outputs
■ Low VCC write inhibit
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
SOFTWARE FEATURES
■ Programmable Burst Interface
■ Supports Common Flash Memory Interface (CFI)
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
■ Software command set compatible with JEDEC 42.4
standards
■ Data# Polling and toggle bits
■ Erase Suspend/Resume
■ Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
— Suspends or resumes an erase operation in one
sector to read data from, or program data to, other
sectors
— Banks A and D each contain four 8 Kword sectors
and thirty-one 32 Kword sectors; Banks B and C
each contain thirty-two 32 Kword sectors
■ Unlock Bypass Program command
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
— Reduces overall programming time when issuing
multiple program command sequences
SRAM Features
■ Power dissipation
■ Minimum 1 million erase cycle guarantee per sector
■ 20-year data retention at 125°C
— Operating: 3 mA maximum
— Standby: 15 µA maximum
PERFORMANCE CHARCTERISTICS
■ Read access times at 54/40 MHz
■ CE1s# and CE2s Chip Select
— Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 1.0 to 2.2 volt
— Asynchronous random access times of 70 ns (at 30
pF)
■ Byte data control: LB#s (DQ7–DQ0), UB#s
(DQ15–DQ8)
— Synchronous latency of 87.5/95 ns
Publication# 26628 Rev: A+1Amendment/+0
Issue Date: December 8, 2002
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