Datasheet > AM45DL32X8G

AM45DL32X8G

更新时间： 2022-01-18 23:27:00

品牌	Logo	应用领域
其他 - ETC		闪存静态存储器
页数	文件大小	规格书
64页	1122K
描述
Am45DL32x8G - Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

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中文翻译

获取价格

数据手册

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AM45DL32X8G 数据手册

P R E L I M I N A R Y

PIN DESCRIPTION

LOGIC SYMBOL

A18–A0

= 19 Address Inputs (Common)

A20–A19, A-1 = 3 Address Inputs (Flash)

A18–A0

= Lowest Order Address Pin (CC

SRAM) Byte mode

A20–A19, A-1

DQ15–DQ0

CE#f

= 16 Data Inputs/Outputs (Common)

= Chip Enable (Flash)

16 or 8

CE#f

DQ15–DQ0

CE#1s

CE2s

= Chip Enable 1 (CC SRAM)

= Chip Enable 2 (CC SRAM)

= Output Enable (Common)

= Write Enable (Common)

= Ready/Busy Output

CE1#s

CE2s

OE#

RY/BY#

OE#

WE#

RY/BY#

UB#s

WP#/ACC

RESET#

UB#s

= Upper Byte Control (CC SRAM)

= Lower Byte Control (CC SRAM)

LB#s

CIOf

= I/O Configuration (Flash)

CIOf = V_IH= Word mode (x16),

CIOf = V_IL= Byte mode (x8)

LB#s

CIOf

CIOs

= I/O Configuration (CC SRAM)

CIOs = V_IH= Word mode (x16),

CIOs = V_IL= Byte mode (x8)

CIOs

RESET#

= Hardware Reset Pin, Active Low

WP#/ACC

= Hardware Write Protect/

Acceleration Pin (Flash)

_CCf

= Flash 3.0 volt-only single power sup-

ply (see Product Selector Guide for

speed options and voltage supply

tolerances)

_CCs

= CC SRAM Power Supply

= Device Ground (Common)

= Pin Not Connected Internally

V_SS

Note: CC = CompactCell^TM.

Am45DL32x8G

August 28, 2002

1...6 7 8910 11 12...64

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